Emil J. Tywoniak
869a7303b0
signorm: disable in passes that use swap_names
2026-03-16 22:45:29 +01:00
Emil J. Tywoniak
3502a51598
opt_expr: fix invert_map
2026-03-13 12:18:48 +01:00
Emil J. Tywoniak
aee094e3c4
fixup! fixup! satgen: support $connect
2026-03-12 22:53:31 +01:00
Emil J. Tywoniak
4d1f8fd7d3
fixup! satgen: support $connect
2026-03-12 22:16:06 +01:00
Emil J. Tywoniak
0d353591fe
satgen: support $connect
2026-03-12 22:15:34 +01:00
Emil J. Tywoniak
ae946a598c
rtlil: add dump_sigmap for hacky signorm debugging
2026-03-12 22:13:21 +01:00
Emil J. Tywoniak
e7a97360a8
techmap: disable signorm more
2026-03-12 22:11:06 +01:00
Emil J. Tywoniak
04311e3e53
techmap: disable signorm
2026-03-11 21:30:27 +01:00
Emil J. Tywoniak
8bad1a2035
opt_hier: disable signorm
2026-03-11 21:26:12 +01:00
Emil J. Tywoniak
4611e90533
timinginfo: disable output wire check due to signorm
2026-03-11 21:25:00 +01:00
Emil J. Tywoniak
44917f50d9
rtlil: forbid rewrite_sigspecs in signorm
2026-03-11 21:07:06 +01:00
Emil J. Tywoniak
d39ce10601
opt_merge_inc: re add initvals deletion
2026-03-11 12:35:16 +01:00
Emil J. Tywoniak
621bb778f5
synth_ice40: always read abc9 model to understand port direction
2026-03-11 12:25:37 +01:00
Emil J. Tywoniak
4c90e26298
tests: adjust to input_port and init behavior (sketchy)
2026-03-10 14:09:31 +01:00
Emil J. Tywoniak
30ac7d271c
satgen: cover $input_port
...
(cherry picked from commit d199195785
2026-03-10 14:06:45 +01:00
Emil J. Tywoniak
c3433bced7
tests: adjust to input_port and init behavior (sketchy)
2026-03-10 14:05:37 +01:00
Emil J. Tywoniak
45a254cf61
tests: adjust to input_port and init behavior (sketchy)
2026-03-10 14:02:46 +01:00
Emil J. Tywoniak
8375f11fa5
wreduce: fixup initvals after setPort
2026-03-10 14:01:57 +01:00
Emil J. Tywoniak
298b755fb7
modtools: fix database sanity on wire name swap
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(cherry picked from commit c75d80905a
2026-03-09 23:46:53 +01:00
Emil J. Tywoniak
58ba984498
ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
2026-03-09 23:38:10 +01:00
Emil J. Tywoniak
25edde1c3c
tests: adjust to input_port and init behavior (sketchy)
2026-03-09 21:21:45 +01:00
Emil J. Tywoniak
d2bc970ef9
rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
2026-03-09 21:20:23 +01:00
Emil J. Tywoniak
bdce610f3d
bug2920: disable
2026-03-09 16:37:30 +01:00
Emil J. Tywoniak
b206223c40
rtlil_bufnorm: fix cell deletion deferral bug
2026-03-07 01:10:04 +01:00
Emil J. Tywoniak
b7c97ba743
tests: adjust to input_port and init behavior (sketchy)
2026-03-07 01:08:57 +01:00
Emil J. Tywoniak
7c5128a08a
check: don't fail on $input_port
2026-03-07 00:42:01 +01:00
Emil J. Tywoniak
c6b9f5d8ff
mem: fix signorm cell type morph
2026-03-07 00:41:24 +01:00
Jannis Harder
eae87b3161
WIP half broken snapshot
2025-10-06 14:39:25 +02:00
Jannis Harder
ea0ee069fb
WIP remove dead code
2025-10-04 14:40:08 +02:00
Emil J
7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops
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Reduce hashops verbiage in `OptMergePass`
2025-09-30 19:34:44 +02:00
Emil J
60c551f961
Merge pull request #5400 from YosysHQ/emil/github-contribution-template-update
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Update contribution templates
2025-09-30 11:03:49 +02:00
Emil J. Tywoniak
dc7764e247
.github: typos
2025-09-30 11:03:19 +02:00
Miodrag Milanović
330a5fc101
Merge pull request #5402 from YosysHQ/micko/extensions
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Force linking log_compat when extensions are linked
2025-09-30 09:10:04 +02:00
Miodrag Milanovic
e6fa0223c8
Force linking log_compat when extensions are linked
2025-09-30 08:44:31 +02:00
github-actions[bot]
5fd2aecd90
Bump version
2025-09-30 00:23:05 +00:00
Emil J. Tywoniak
b86cc0d9b3
docs: replace Slack with Discourse in extensions writing guide
2025-09-29 23:20:06 +02:00
Emil J. Tywoniak
b2adaeec69
.github: replace Slack and GitHub Discussions with Discourse in issue templates
2025-09-29 23:03:54 +02:00
Emil J. Tywoniak
4c17ac5ac2
.github: suggest Discourse in PR template
2025-09-29 23:03:29 +02:00
ShinyKate
30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff
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read_blif: Represent sequential elements with gate cells
2025-09-29 08:21:16 -05:00
Jannis Harder
47639f8a98
Merge pull request #5388 from jix/bufnorm-followup
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Refactor and fixes to incremental bufNormalize + related changes
2025-09-29 15:15:29 +02:00
Jannis Harder
6a7372626a
Merge pull request #5389 from jix/sva_continue
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verific: New `-sva-continue-on-error` import option
2025-09-29 15:07:54 +02:00
Emil J
87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic
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Move `OptMerge` cell filtering logic to happen while building the cell vector
2025-09-29 15:03:01 +02:00
Martin Povišer
04c7013f0e
Merge pull request #5399 from povik/opt_hier-bug
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opt_hier: Fix two optimizations conflicting
2025-09-29 14:53:54 +02:00
Akash Levy
acf3a6606f
Small gitignore fixes
2025-09-29 12:11:59 +01:00
Martin Povišer
a9318db2fa
opt_hier: Adjust messages
2025-09-29 12:27:27 +02:00
Martin Povišer
ffe2f7a16d
opt_hier: Fix two optimizations conflicting
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Fix a conflict between the following two:
* propagation of tied-together inputs in
* propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Miodrag Milanović
69770a844e
Merge pull request #5396 from akashlevy/pyosys_fix
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BUGFIX: pyosys cannot parse header with omitted function args
2025-09-29 10:20:31 +02:00
Jannis Harder
86fb2f16f7
bufnorm: Refactor and fix incremental bufNormalize
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This fixes some edge cases the previous version didn't handle properly
by simplifying the logic of determining directly driven wires and
representatives to use as buffer inputs.
2025-09-29 08:21:28 +02:00
Jannis Harder
cbc1055517
opt_clean: Fix debug output when cleaning up bufnorm cells
2025-09-29 08:21:28 +02:00
Jannis Harder
90669ab4eb
aiger2: Only fail for reachable undirected bufnorm helper cells
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The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.
Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.
With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
2025-09-29 08:21:28 +02:00
