antonblanchard.microwatt

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602ba25c70 Metavalue cleanup for decoder1.vhdl Michael Neuling 2022-07-14 10:30:57 +10:00
7656abd765 Metavalue cleanup for helpers.vhdl Michael Neuling 2022-07-14 10:29:11 +10:00
caf458be37 Metavalue cleanup for common.vhdl Michael Neuling 2022-07-28 09:50:26 +10:00
281a125f1f Merge pull request #379 from paulusmack/master Michael Neuling 2022-07-26 10:08:33 +10:00
bad9a9a2e8 Merge pull request #380 from iagocaran/master Michael Neuling 2022-07-25 16:31:12 +10:00
a060ad5085 tests/pmu: Cleanup whitespace in pmc.c Michael Neuling 2022-07-25 15:03:40 +10:00
d6121cd636 Use register addresses from decode1 for dependency tracking Paul Mackerras 2022-07-14 15:47:21 +10:00
1d7de2f1da register_file: Make read access to register file synchronous Paul Mackerras 2022-02-22 09:30:05 +11:00
06c13d4988 decode1: Work out register addresses in decode1 Paul Mackerras 2022-02-21 19:29:09 +11:00
047be5c0c3 loadstore1: Do SPR reading in stage 2 rather than stage 3 Paul Mackerras 2022-03-23 18:02:28 +00:00
af814a0d5e Provide debug access to SPRs in loadstore1 and mmu Paul Mackerras 2022-02-24 11:37:17 +11:00
d0f319290f Restore debug access to SPRs Paul Mackerras 2022-02-25 16:46:34 +11:00
fdb3ef6874 Finish off taking SPRs out of register file Paul Mackerras 2022-02-19 19:03:49 +11:00
337b104250 Move LR, CTR and TAR out of the register file Paul Mackerras 2022-07-12 11:20:17 +10:00
bc4d02cb0d Start removing SPRs from register file Paul Mackerras 2022-07-12 08:52:05 +10:00
73cc5167ec Use FPU for division instructions if we have an FPU Paul Mackerras 2022-05-09 19:18:42 +10:00
34330552e8 FPU: Add logic for 32-bit integer division Paul Mackerras 2022-05-07 22:34:23 +10:00
a95f8aab38 FPU: Add integer division logic to FPU Paul Mackerras 2022-05-07 18:28:33 +10:00
23d5c4edc5 FPU: Convert internal R, A, B, and C registers to 8.56 format Paul Mackerras 2022-05-02 09:39:26 +10:00
d1850fea29 Track hazards explicitly for XER overflow bits Paul Mackerras 2022-07-09 18:29:48 +10:00
7c240a664b fetch1: Fix debug stop again Paul Mackerras 2022-07-09 13:17:18 +10:00
e598c2aef8 control: Reimplement serialization using tags Paul Mackerras 2022-07-09 11:55:13 +10:00
2da08bcf2e decode1: Remove stash buffer Paul Mackerras 2022-07-08 16:37:12 +10:00
2f45e545ed decode2: Rework to make the stall_out signal come from a register Paul Mackerras 2022-07-08 14:07:28 +10:00
c9e838b656 Remove support for lq, stq, lqarx and stqcx. Paul Mackerras 2022-06-04 17:37:48 +10:00
0bd1e24024 decode2: Rename 'r' to 'dc2' Paul Mackerras 2022-07-04 18:23:03 +10:00
ebe1caab85 decode1: Reduce number of single-issue instructions Paul Mackerras 2022-07-02 22:23:35 +10:00
9a8a8e50f8 FPU: Add stage-2 stall ability to FPU Paul Mackerras 2022-07-02 14:17:18 +10:00
ef122868d5 Do CR0 setting for Rc=1 instructions in execute2 instead of writeback Paul Mackerras 2022-06-28 18:18:08 +10:00
e030a500e8 Allow integer instructions and load/store instructions to execute together Paul Mackerras 2022-06-27 18:53:04 +10:00
4b6148ada6 Add a bypass path from the execute2 stage Paul Mackerras 2022-06-28 08:40:42 +10:00
3510071d9a Add a second execute stage to the pipeline Paul Mackerras 2022-06-30 20:33:33 +10:00
521a5403a9 execute1: Rename 'r' to 'ex1' Paul Mackerras 2022-06-18 17:29:43 +10:00
813e2317bf execute1: Restructure to separate out execution of side effects Paul Mackerras 2022-06-18 16:24:30 +10:00
de1bf10114 tests/pmu: Add load/store completed, instruction count and cycle count tests Iago Caran Aquino 2022-07-19 17:24:14 -03:00
204fedc63f Move XER low bits out of register file Paul Mackerras 2022-06-29 20:02:36 +10:00
bdd4d04162 Simplify flow control in the dcache and loadstore units Paul Mackerras 2022-06-11 19:20:57 +10:00
35e0dbed34 Merge pull request #353 from tianrui-wei/master Paul Mackerras 2022-06-17 09:46:57 +10:00
cd52390bf1 Merge pull request #373 from antonblanchard/icache-insn-u-state Michael Neuling 2022-06-17 09:13:49 +10:00
b983d5080e Merge pull request #376 from antonblanchard/loadstore-init Michael Neuling 2022-06-16 16:47:33 +10:00
d4db331467 Merge pull request #374 from antonblanchard/icache-unused-sig Michael Neuling 2022-06-16 16:45:41 +10:00
ee5e3778ed Merge pull request #364 from shenki/readme-updates Michael Neuling 2022-06-16 14:38:12 +10:00
c43692f4c7 Merge pull request #372 from antonblanchard/dcache-unused-sig Michael Neuling 2022-06-16 14:36:50 +10:00
956df2c863 Merge pull request #371 from antonblanchard/unused-sig Michael Neuling 2022-06-16 14:35:10 +10:00
3627f102db Merge pull request #370 from antonblanchard/divider-init Michael Neuling 2022-06-16 14:33:45 +10:00
6e1e763c02 Merge pull request #368 from antonblanchard/icache-pmu-events Paul Mackerras 2022-06-15 11:02:58 +10:00
1047239a37 Merge pull request #377 from antonblanchard/fpu-init Anton Blanchard 2022-06-14 18:10:37 +10:00
9d35340bb1 fpu: Reduce uninitialised signals fpu-init Anton Blanchard 2022-06-14 15:14:19 +10:00
b82eea5933 Merge pull request #366 from antonblanchard/hello-world-bss Michael Neuling 2022-06-14 13:09:57 +10:00
d3aff67fa7 Merge pull request #375 from antonblanchard/core_debug-init Anton Blanchard 2022-06-13 07:15:55 +10:00
b47b71821e loadstore1: reduce U state being output loadstore-init Anton Blanchard 2022-06-12 22:15:11 +10:00
71d4b5ed20 core_debug: Initialise gspr_index core_debug-init Anton Blanchard 2022-06-12 21:49:13 +10:00
a527d9b959 core: Remove unused icache_inv signal icache-unused-sig Anton Blanchard 2022-06-12 21:04:16 +10:00
e7f0a7c7ac icache: Don't output X on i_out.insn icache-insn-u-state Anton Blanchard 2022-06-12 11:42:32 +10:00
39220be311 dcache: remove unused do_write signal dcache-unused-sig Anton Blanchard 2022-06-12 11:39:31 +10:00
843361f2be execute1: sub_mux_sel and result_mux_sel are unused unused-sig Anton Blanchard 2022-06-12 10:49:26 +10:00
d3a7517318 divider: Fix d_out.overflow U state issue divider-init Anton Blanchard 2022-06-12 10:34:20 +10:00
1ff852b012 Merge pull request #369 from antonblanchard/loadstore-pmu-init Anton Blanchard 2022-06-12 10:24:54 +10:00
e2438071a1 loadstore1: Initialise PMU events loadstore-pmu-init Anton Blanchard 2022-06-12 09:29:46 +10:00
b7c4d3c5c3 Merge pull request #367 from antonblanchard/fpu-typo Anton Blanchard 2022-06-12 09:32:59 +10:00
f06abb67ad icache: Hook up PMU events icache-pmu-events Anton Blanchard 2022-06-12 09:21:56 +10:00
64d2def0c6 fpu: Fix capitalisation of Execute1ToFPUType fpu-typo Anton Blanchard 2022-06-10 08:10:27 +10:00
ff442d1bdb Zero BSS in hello world test Anton Blanchard 2022-06-08 15:20:07 +10:00
b8fc5636a4 Merge pull request #365 from antonblanchard/less-fpga-init Anton Blanchard 2022-06-08 14:54:48 +10:00
ebdddcc402 Remove some FPGA style signal inits less-fpga-init Anton Blanchard 2022-06-07 20:01:14 +10:00
a750365ffa Remove some FPGA style signal inits Anton Blanchard 2022-06-07 17:38:24 +10:00
9ec22af256 README: Add Linux on Microwatt instructions Joel Stanley 2022-06-07 12:50:03 +09:30
a31725d989 README: Add uart to fusesoc instructions Joel Stanley 2022-06-07 12:48:42 +09:30
2083bc3ed0 ASIC: Fix multiplier power caravel-mpw6-20220530 Anton Blanchard 2022-06-07 08:50:35 +10:00
ace41e5153 ASIC: Reduce multiplier from 4 to 2 cycles Anton Blanchard 2022-05-30 14:34:21 +10:00
907c833521 Move register stage back after the RAM caravel-mpw5-20220323 Anton Blanchard 2022-03-23 17:43:09 +11:00
f5e06c2d4b Merge pull request #361 from antonblanchard/alt-reset-address Michael Neuling 2022-03-22 11:55:54 +11:00
5c40143754 Add a script to post process the Microwatt verilog for caravel caravel-mpw5-20220322 Anton Blanchard 2020-12-17 15:14:54 +11:00
d0ced7441f Add simplebus verilog Anton Blanchard 2022-03-21 06:35:38 +11:00
606359cce3 Add simplebus Anton Blanchard 2022-03-15 15:19:13 +11:00
49b332e17f Hook up JTAG to ASIC top level Anton Blanchard 2021-10-26 15:15:02 +11:00
d5e3be80fe Set a unique PVR for caravel MPW5 Anton Blanchard 2021-01-14 10:21:33 +11:00
d504ae63f6 Update JTAG TAP controller for Microwatt Anton Blanchard 2020-12-08 18:55:08 +11:00
15bb4aa90a First pass at an external JTAG port Anton Blanchard 2022-02-01 08:44:00 +11:00
c2577b5446 Add ASIC target Anton Blanchard 2021-03-24 22:00:27 +11:00
5249d633cf Move register stage from after RAM to before RAM Anton Blanchard 2022-02-24 10:18:28 +11:00
8ecb30da05 Add arrays for ASIC flow Anton Blanchard 2021-03-23 19:44:16 +11:00
747c96b100 Cut down hello_world to fit in 4kB Anton Blanchard 2021-10-26 12:21:26 +11:00
faab169307 Allow ALT_RESET_ADDRESS to be overridden Anton Blanchard 2022-02-01 20:06:57 +11:00
948f6f43a7 Allow ALT_RESET_ADDRESS to be overridden alt-reset-address Anton Blanchard 2022-03-22 09:35:17 +11:00
8bf48ac094 Merge pull request #360 from antonblanchard/log2ceil-issue Michael Neuling 2022-03-18 18:28:34 +11:00
b5accb78b2 wishbone_bram_wrapper ram_addr_bits is 1 bit off log2ceil-issue Anton Blanchard 2022-03-17 18:03:29 +11:00
30fd936c12 Merge pull request #358 from antonblanchard/unused-sig Michael Neuling 2022-03-16 10:49:47 +11:00
af1b76d944 Merge pull request #356 from antonblanchard/fpu-constant Michael Neuling 2022-03-16 10:49:29 +11:00
9b96ab730c Merge pull request #357 from antonblanchard/xics-warning Michael Neuling 2022-03-16 10:48:59 +11:00
0b39947f8d Remove unused sequential signal from Fetch1ToIcacheType Anton Blanchard 2022-03-15 18:27:48 +11:00
00bf0af21c xics: Fix warning when comparing two std_ulogic_vectors Anton Blanchard 2022-03-15 16:04:18 +11:00
50b4cb9423 fpu: Make inverse_table a constant fpu-constant Anton Blanchard 2022-03-15 16:03:34 +11:00
844ca0e6b5 fix: fix icache_tb not finishing correctly Tianrui Wei 2022-03-01 23:51:35 +08:00
f01f3d233a Merge pull request #352 from mkj/static-urjtag Michael Neuling 2022-02-28 08:17:50 +11:00
c0c00d05bc mw_debug: Add STATIC_URJTAG flag Matt Johnston 2022-02-25 17:43:28 +08:00
ffcdaaa92d Update the README Issues (#350) Michael Neuling 2022-02-25 13:18:38 +11:00
b4770197a2 Merge pull request #349 from madscientist159/master Michael Neuling 2022-02-25 11:08:57 +11:00
fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line Raptor Engineering Development Team 2022-02-22 11:49:33 -06:00
2b97fb0bf3 Merge pull request #348 from paulusmack/reduce Michael Neuling 2022-02-23 12:03:59 +11:00

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