antonblanchard.microwatt

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f812832ad7 dcache: Move way selection and forwarding earlier Paul Mackerras 2021-08-28 20:11:55 +10:00
a9e6263aab Merge pull request #319 from antonblanchard/verilator-ci Michael Neuling 2021-08-17 12:31:12 +10:00
8bbb0018b4 Merge pull request #318 from paulusmack/pmu Michael Neuling 2021-08-16 13:08:24 +10:00
05fe709ffc Merge pull request #320 from antonblanchard/litedram-regenerate Michael Neuling 2021-08-16 09:23:27 +10:00
c0f7f54276 litedram: Regenerate from upstream litex Anton Blanchard 2021-08-15 06:20:22 +10:00
ee38a31152 ci: Add verilator tests Anton Blanchard 2021-08-14 18:25:15 +10:00
c81583c128 makefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE Anton Blanchard 2021-08-14 19:34:12 +10:00
efb387b0d2 makefile: Add some verilator micropython tests Anton Blanchard 2021-08-14 16:59:50 +10:00
8acd5a5607 verilator: Specify top level module Anton Blanchard 2021-08-14 15:03:16 +10:00
7e2de602ee makefile: Simplify microwatt-verilator target, add Docker image Anton Blanchard 2021-08-13 15:04:06 +10:00
65c43b488b PMU: Add several more events Paul Mackerras 2021-08-13 19:29:48 +10:00
8cdb00652b Merge pull request #316 from antonblanchard/verilator-fix Paul Mackerras 2021-08-14 10:18:42 +10:00
71af8016da Merge pull request #317 from antonblanchard/gpio-fix Paul Mackerras 2021-08-14 10:18:12 +10:00
e33fb26e7a PMU: Fix PMC5/6 behaviour when MMCR0[PMCC] = 11 Paul Mackerras 2021-08-11 17:17:25 +10:00
591e96d1a2 gpio: Add HAS_GPIO to avoid verilator build errors Anton Blanchard 2021-08-13 14:44:04 +10:00
bc0f7cf236 Rename 'do' signal to avoid verilator System Verilog warning Anton Blanchard 2021-08-13 13:52:51 +10:00
2bd00f5119 Merge pull request #315 from paulusmack/pmu Michael Neuling 2021-08-12 08:24:05 +10:00
1d29cdcfb4 Remove Potato UART remove-potato-uart Anton Blanchard 2021-08-11 17:44:54 +10:00
1896e5f803 Merge pull request #314 from antonblanchard/yosys-go-fast-bits Paul Mackerras 2021-08-11 16:26:29 +10:00
400e481ffa Merge pull request #313 from paulusmack/fixes Michael Neuling 2021-08-11 16:25:35 +10:00
a7873b45f7 core: Add a basic performance monitor unit (PMU) implementation Paul Mackerras 2021-04-26 18:09:48 +10:00
6254bb5ee9 Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut Anton Blanchard 2021-08-11 14:34:41 +10:00
aa4e4e77c4 Merge pull request #311 from antonblanchard/litesdcard-nexys-video Michael Neuling 2021-08-11 09:48:07 +10:00
65c131e89f Merge pull request #312 from shenki/sdcard-soc-features Michael Neuling 2021-08-11 09:33:36 +10:00
f40842d9b2 tests/fpu: Test FPU unavailable interrupt following a load Paul Mackerras 2021-05-26 17:44:19 +10:00
bc3995804f litedram: Add sdcard to soc features Joel Stanley 2021-08-10 18:49:29 +09:30
64e3ce7134 execute1: Handle interrupts during sequences of load/store operations Paul Mackerras 2021-05-26 17:34:12 +10:00
7cfbcd5514 litesdcard: Add Nexys Video support Anton Blanchard 2021-08-10 06:41:45 +10:00
9caaa3fc46 litesdcard: Use vendor not board type Anton Blanchard 2021-08-10 06:37:09 +10:00
c198b2b82e Merge pull request #310 from antonblanchard/liteeth-update-2 Paul Mackerras 2021-08-10 14:04:55 +10:00
34e10cc52c liteeth: Regenerate from upstream litex Anton Blanchard 2021-08-09 13:55:58 +10:00
12efb51bcc liteeth: Update yaml config Anton Blanchard 2021-08-09 13:49:25 +10:00
458dfe01a6 Add liteeth support to Nexys Video Anton Blanchard 2021-08-04 15:59:43 +10:00
cf6df4f17f Merge pull request #307 from antonblanchard/litedram-update Michael Neuling 2021-08-09 15:42:05 +10:00
69a1440204 Merge pull request #309 from antonblanchard/clk-cleanup Michael Neuling 2021-08-09 15:31:09 +10:00
b885ee7ed1 Merge pull request #308 from antonblanchard/small-fixes Michael Neuling 2021-08-09 14:25:06 +10:00
75e06a1e30 Remove -add from xdc files Anton Blanchard 2021-08-09 13:26:32 +10:00
187199c489 Remove -waveform from xdc files Anton Blanchard 2021-08-09 13:02:01 +10:00
7994b98404 Fix some whitespace issues Anton Blanchard 2021-08-09 06:44:43 +10:00
46cde3bb23 Merge pull request #305 from mikey/noflatten Anton Blanchard 2021-08-09 11:28:49 +10:00
780d6c754c litedram: Regenerate from upstream litex Anton Blanchard 2021-08-09 10:54:35 +10:00
07f2edc415 litedram: sdrinit() is now sdram_init() Anton Blanchard 2021-08-09 10:53:51 +10:00
346686feb8 litedram: Fix compiler warning Anton Blanchard 2021-08-09 10:29:48 +10:00
ac546a3024 litedram: Update yaml files Anton Blanchard 2021-08-09 10:26:35 +10:00
6034a9e31f litedram: simplify generate.py Anton Blanchard 2021-08-09 10:24:38 +10:00
3275304a7f litedram: Remove variables.mak Anton Blanchard 2021-08-09 09:49:03 +10:00
d6efbb327f ci: Remove noflatten to reduce size of ECP5 builds Michael Neuling 2021-08-04 16:33:52 +10:00
0199ff8ca8 Merge pull request #299 from mikey/vunit-make Anton Blanchard 2021-08-04 13:59:22 +10:00
25ab1053e9 Merge pull request #304 from umarcor/ci-backends Michael Neuling 2021-08-04 09:57:35 +10:00
de41dfc703 ci: test 'build' with LLVM and GCC backends umarcor 2021-07-22 00:02:41 +02:00
0cd826d190 Merge pull request #301 from umarcor/vunit-cleanup Michael Neuling 2021-08-02 14:22:11 +10:00
bf76261979 makefile: Add check_vunit Michael Neuling 2021-06-21 11:35:56 +10:00
178c2a7da3 VUnit: style umarcor 2021-07-21 19:54:27 +02:00
2031c6d2d2 VUnit: use Path.glob instead of glob.glob umarcor 2021-07-21 19:52:24 +02:00
7571416f81 ci: add 'workflow_dispatch' umarcor 2021-07-21 18:09:37 +02:00
faf8309629 ci: in job 'VUnit' use a container step instead of a container job umarcor 2021-07-21 18:04:15 +02:00
d7458d5beb Reduce the size of icache to help yosys ECP5 builds (#303) Michael Neuling 2021-07-31 11:18:39 +10:00
f9654428ff Merge pull request #296 from LarsAsplund/logging-checking Michael Neuling 2021-06-21 17:58:34 +10:00
9e3c756234 Merge pull request #298 from paulusmack/master Michael Neuling 2021-06-21 11:51:13 +10:00
ff7421c54e Merge pull request #295 from LarsAsplund/master Michael Neuling 2021-06-21 11:25:40 +10:00
18120f153d MMU: Implement a vestigial partition table Paul Mackerras 2021-06-17 20:01:32 +10:00
478b787c10 Replaced VHDL assert and report with VUnit checking and logging Lars Asplund 2021-06-09 23:50:02 +02:00
0865704e21 Run VUnit tests in CI Lars Asplund 2021-06-09 16:19:24 +02:00
0940b8a9d3 Organized VUnit testbenches into test cases. Lars Asplund 2021-06-08 22:32:57 +02:00
08c0c4c1b4 Make core testbenches recognized by VUnit Lars Asplund 2021-06-07 22:34:00 +02:00
41d57e6148 Added VUnit run script. Lars Asplund 2021-06-07 22:05:57 +02:00
84473eda1b Merge pull request #277 from paulus/gpio Michael Neuling 2021-05-17 16:19:47 +10:00
7f44980611 Merge pull request #287 from paulusmack/master Michael Neuling 2021-05-14 09:11:41 +10:00
d8ea64675a Merge pull request #278 from shenki/openocd-v0.11 Paul Mackerras 2021-05-11 20:25:29 +10:00
0d4a0bab6e openocd: Fix verify command for v0.10 Joel Stanley 2021-05-11 14:17:26 +09:30
21ed730514 arty_a7: Add litesdcard interface Paul Mackerras 2021-04-15 17:22:31 +10:00
231003f7c7 icache: Snoop writes to memory by other agents Paul Mackerras 2021-05-11 14:04:08 +10:00
4c11c9c661 dcache: Simplify logic in RELOAD_WAIT_ACK state Paul Mackerras 2021-05-11 11:29:46 +10:00
eb7eba2d92 dcache: Snoop writes to memory by other agents Paul Mackerras 2021-05-11 10:54:57 +10:00
4a8ab3331c Merge pull request #283 from antonblanchard/whitespace Paul Mackerras 2021-05-05 10:20:46 +10:00
d9a398dc81 Update documentation. (#280) Antony Vennard 2021-05-05 02:15:26 +02:00
6d827b9358 Merge pull request #286 from antonblanchard/Makefile-cleanup-3 Anton Blanchard 2021-03-25 14:43:45 +11:00
be11ebbf6d Remove unused GHDL_TARGET_GENERICS Anton Blanchard 2021-03-25 14:05:00 +11:00
33c78f9282 Move verilator --trace flag into VERILATOR_FLAGS Anton Blanchard 2021-03-24 21:40:26 +11:00
0af906232f Merge pull request #285 from antonblanchard/Makefile-cleanup-2 Anton Blanchard 2021-03-24 21:31:54 +11:00
5cc5d8f030 Merge pull request #281 from antonblanchard/cache-tlb-parameters Anton Blanchard 2021-03-24 20:44:45 +11:00
4ab36517ec Remove -frelaxed Anton Blanchard 2021-03-24 17:08:29 +11:00
561d6af6f0 Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator targets Anton Blanchard 2021-03-24 17:07:56 +11:00
75da4156fe Remove core_files from soc_files and fpga_files Anton Blanchard 2021-03-24 15:08:18 +11:00
ef01fa32bd Merge pull request #284 from antonblanchard/boot-clocks Anton Blanchard 2021-03-23 20:02:27 +11:00
53ccf89d26 Use a record for cache parameters cache-tlb-parameters-2 Anton Blanchard 2021-03-23 10:32:25 +11:00
af462f0ca9 Reformat spi_flash_ctrl Anton Blanchard 2021-03-22 11:01:10 +11:00
2db89628ab Reformat control Anton Blanchard 2021-03-22 10:55:53 +11:00
21f482f967 Reformat testbenches Anton Blanchard 2021-03-22 10:55:32 +11:00
0d86580ac7 Reformat writeback Anton Blanchard 2021-03-22 10:19:27 +11:00
f67b143165 Reformat plru Anton Blanchard 2021-03-22 10:17:49 +11:00
c76e638a77 Reformat rotator Anton Blanchard 2021-03-22 10:09:39 +11:00
601f3211be Reformat divider Anton Blanchard 2021-03-22 10:08:29 +11:00
bf96279ff1 Reformat countzero Anton Blanchard 2021-03-22 10:07:47 +11:00
af7e330d69 Reformat cr_file Anton Blanchard 2021-03-22 10:07:33 +11:00
9208276aa2 Reformat register_file Anton Blanchard 2021-03-22 10:06:03 +11:00
74254bf11a Reformat cache_ram Anton Blanchard 2021-03-22 09:56:12 +11:00
91a53d8001 Allow SPI BOOT_CLOCKS to be overridden by top level Anton Blanchard 2021-03-15 20:03:45 +11:00
2d21b95f87 Pass icache/dcache/tlb parameters down from soc Anton Blanchard 2021-03-15 18:18:21 +11:00
f06a0f4e5a arty: Update GPIOs for Boxarty BMC Paul Mackerras 2021-03-09 13:16:28 +11:00

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