github.com/j-core.j-core-ice40
1
0
Fork 0
mirror of https://github.com/j-core/j-core-ice40.git synced 2026-03-09 20:18:40 +00:00
Code Issues Releases Wiki Activity
31 Commits 1 Branch 0 Tags
53246c4690e8ea306bd02a0e04b352e58619ff46
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
J 53246c4690 Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu
2019-04-02 16:18:02 -04:00
synth
Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu
2019-04-02 16:18:02 -04:00
testrom
Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead
2019-04-01 17:45:50 -04:00
asymmetric_ram.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
bus_monitor.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
clk_sim.vhd
Actually add sim model for Lattice HF clk
2019-03-08 01:10:20 -05:00
components_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
conv.c
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
cpu2j0_pkg.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
cpu_bulk_sram.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
cpu_lattice.vhd
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
cpu_pure_tb.vhh
With single port RAM
2019-03-03 23:16:35 -05:00
cpu_simple_sram.vhd
With single port RAM
2019-03-03 23:16:35 -05:00
cpu_sram.vhd
Add testrom, modified for small memory... enable tests if you need in Makefile
2019-03-03 20:55:24 -05:00
cpu_up5k_42s.vhd
Minor change to pinouts for v1.1 board
2019-03-26 12:05:44 -04:00
cpu.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
data_bus_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
datapath_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
datapath.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
decode_body.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode_core.vhd
Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu
2019-04-02 16:18:02 -04:00
decode_pkg.vhd
Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used
2019-03-03 17:29:03 -05:00
decode_table_reverse.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode_table_rom.vhd
Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu
2019-04-02 16:18:02 -04:00
decode_table.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
decode.vhd
Sync RAM register file implemntation
2019-03-13 17:05:56 -04:00
free42.pcf
Minor change to pinouts for v1.1 board
2019-03-26 12:05:44 -04:00
ghdl_lattice.sh
Bring over ROM decoder version. Sim is correct, synth is 10% smaller doesn't boot. This CPU corresponds ~rev 745:b529b2d1c276 of SEI internal repos soc_top/components/cpu
2019-04-02 16:18:02 -04:00
ghdl_up5k.sh
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
ghdl.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
lattice_ebr.vhd
A few warnings fixed
2019-03-13 19:40:04 -04:00
lattice_spr_wrap.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
lattice_spr.vhd
With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.
2019-03-25 21:50:49 -04:00
lattice_tb.vhd
Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk
2019-03-08 01:09:52 -05:00
monitor_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult_pkg.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
mult.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
nvc_lattice.sh
Add sim by default and wave viewer ctl file for reg file debug
2019-03-08 01:37:20 -05:00
nvc_simple.sh
With single port RAM
2019-03-03 23:16:35 -05:00
nvc.sh
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
ram_init.vhd
Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead
2019-04-01 17:45:50 -04:00
ram.img
Cosmetic... print key names. RAM full, use rev 28 for block ram checking instead
2019-04-01 17:45:50 -04:00
ram.sh
First synthesys for ICE40 UP5k with everything to blink LEDs
2019-03-04 01:17:33 -05:00
reg.gtkw
Attempt to avoid write conflict on Lattice EB RAM
2019-03-15 16:46:15 -04:00
register_file_sync.vhd
Attempt to avoid write conflict on Lattice EB RAM
2019-03-15 16:46:15 -04:00
register_file.vhd
Sync RAM register file implemntation
2019-03-13 17:05:56 -04:00
simple_ram.vhd
With single port RAM
2019-03-03 23:16:35 -05:00
timeout_cnt.vhd
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
up5k_tb.vhd
Minor change to pinouts for v1.1 board
2019-03-26 12:05:44 -04:00
upduino2.pcf
Continue simple cleanups of pinouts and platform split. Still doesn't work, though
2019-03-27 21:04:53 -04:00
verific
Import from the git version found in work/nickg on my trash can mac
2019-03-03 14:48:57 -05:00
Description
J-core SOC for ice40 FPGA
379 KiB
Languages
VHDL 75.2%
Assembly 14.1%
C 9.3%
Shell 0.8%
Linker Script 0.3%
Other 0.3%