Unified BIOS Patching: Merged management for SCPH-5500, 5000, and 3500.
New Hardware Bypass: Added a physical switch option for SCPH-7000 to disable the BIOS patch on-the-fly.
Compilation Feedback: Integrated #pragma messages to display during the build process.
Code Documentation: improved technical clarity.
Re-implemented Hardware ISR (INT0/INT1): Restored interrupt-driven pulse counting to eliminate polling jitter. Tests confirmed that at 16MHz, software polling is too inconsistent for reliable DATA OVERDRIVE synchronization.
Mechanism Freeze: The core logic (Stabilization -> Silence Detection -> ISR Counting -> Injection) is now finalized and stable.
Portability Note: Maintained a clean structure to allow future non-ISR porting, although the ISR version remains the mandatory standard for ATmega328P @ 16MHz performance.
New 2-phase sync (Stabilization + Silence detection).
Refactored GPIO macros for faster execution.
Cleaned up SCPH model definitions and fixed backslash warnings.
Removed unused global variables to save RAM.
Removal of ISR and reduction of code in the BIOS patch, for improved portability and robustness.
For now it is only available for the SCPH-100 and 102.
removal of the ISR(CTC_TIMER_VECTOR) function, and all its dependencies.
- Timer_Start
- Timer_Stop
modification
- Board detection
- inject_SCEX
- BIOS_PATCH
- MCU
- Setting