1
0
mirror of https://github.com/livingcomputermuseum/cpus-pdp8.git synced 2026-02-26 17:04:27 +00:00

Commit Graph

  • efc8f9db2b Fix for TC08 dectape support: Forgot that the TC08 uses three-cycle databreak; addresses 7754 and 7755 are used to support this. Moved RKSYS code out of this area to avoid conflict. master Josh Dersch 2019-12-11 15:53:16 -08:00
  • 77866b7b65 Initial fixes for TC08 code -- hardcoded addresses in dectape code cause RK05 swap code to be overwritten. These have been corrected but something is still touching address 7754 in field 0 when it should not. Josh Dersch 2019-12-10 18:12:01 -08:00
  • 18d8363c9a TS8 assembly broken with EAE enabled, bootstrap routine for RK05 was too large. Ensmallened code in BOOT. Josh Dersch 2019-11-26 14:38:50 -08:00
  • 0c2e7678c4 Update README.md Living Computers: Museum+Labs 2019-11-25 15:49:46 -08:00
  • 8956030516 Update README.md Living Computers: Museum+Labs 2019-11-25 12:33:26 -08:00
  • 86c978efc6 Merge branch 'master' of https://github.com/livingcomputermuseum/cpus-pdp8 Josh Dersch 2019-11-25 12:27:41 -08:00
  • e1fc30f45c Adding assembler listings to repo. Josh Dersch 2019-11-25 12:27:09 -08:00
  • bc3403e519 Update README.md Living Computers: Museum+Labs 2019-11-25 12:26:23 -08:00
  • acee4bd03b Update README.md Living Computers: Museum+Labs 2019-11-25 12:24:30 -08:00
  • a31b083cdd Removing files unrelated to tss-8 (Brad's vhdl, cpu sim, etc.). Adding clean LCM disk image with software loaded. Small cleanup to ts8.pal. Josh Dersch 2019-11-25 11:48:19 -08:00
  • 38191a07c6 Fixed free core map for RKSYS-related blocks. Hopefully. Cleaned up some naming, removed some TODOs. Josh Dersch 2019-11-24 17:03:43 -08:00
  • 134c021505 Minor fix, disabling echoing by monitor in LISP. Josh Dersch 2019-11-23 23:19:30 -08:00
  • 47fba92a6c Ported LISP-8 (DECUS-8-102A-PB) to TSS-8 (fixed entrypoint, added restart address). Josh Dersch 2019-11-23 17:39:12 -08:00
  • 858519f4bf Added RK8E bootstrap to ts8.pal. This allows quick rebooting (assuming core is intact) from address 3053 in field 0. (Ensure AC, IF, and DF are clear beforehand.) Josh Dersch 2019-11-22 23:18:43 -08:00
  • d5b8016c4f Ported CHEKMO-II to TSS/8. Josh Dersch 2019-11-21 15:58:00 -08:00
  • 0144a3523d Adding the first of a few programs to be ported to TSS/8 Josh Dersch 2019-11-21 15:54:22 -08:00
  • 2ddaf0d205 Added patch to maker.c; updates INIT for a 50Hz clock (as used on the M8330). Frank 2019-11-20 19:43:58 -08:00
  • 20f6e172cb Modified filesystem size to the maximum permissable by the TSS/8 filesystem code, approx. 1mw. Updated system to include TC08 and high-speed papertape reader/punch. Frank 2019-11-20 13:28:52 -08:00
  • 3987c3da16 Added small RK05 bootstrap (to avoid needing to load INIT in via papertape every time). This loads INIT from track 2 of the RK05 and starts it. Josh Dersch 2019-11-18 14:38:07 -08:00
  • ab1b026866 Filesystem disk reads/writes are now retryable on error. Retrying tested via instrumented code. Frank 2019-11-17 22:39:04 -08:00
  • a726d29efd Minor updates to ts8.pal; we now explicitly check for rk8e disk address overflow (should never happen). Frank 2019-11-17 13:35:20 -08:00
  • 90c4ec6687 Fixed issue with track # translation to RK8E disk address for one of the two swap paths; this was causing the bizarre behavior when TSS/8 ran out of core. Some minor cleanup. Frank 2019-11-17 00:54:33 -08:00
  • ea7b705dc0 Fix in RK05 SWAP routines (incorrect return from calls to SWPIO), this fixes the random delay when exiting from programs. Frank 2019-11-16 00:35:16 -08:00
  • f25d0c95be Interim fix for disk address calculation in RKGO0, I forgot about that whole "link bit" thing and the "rotate" thing with RTL. Whoops. BASIC runs a lot better now that it's not reading garbage into memory. Josh Dersch 2019-11-15 18:53:57 -08:00
  • 9dce55ea3a Many tiny fixes. TSS/8 now runs from RK05! Long delay on program exit; suspect hung device. Josh Dersch 2019-11-14 18:16:12 -08:00
  • 0664d7d2f4 Further debugging and refinement. Discovered that the free core table in INIT clobbers parts of field 1; this occurs on a clean tss8.2 build as well. Stubbed out all but the first core free (which frees the majority of unused space in field 1), needs to be more deeply investigated. Josh Dersch 2019-11-13 17:45:52 -08:00
  • 8d867d46be Bugfixes, getting closer. Josh Dersch 2019-11-12 17:01:09 -08:00
  • f963522e53 Rough, untested implementation of filesystem read/write routines for RK8E. Josh Dersch 2019-11-11 17:53:55 -08:00
  • f2b2cdf6cf Started work on DS routines for RK05. Frank 2019-11-10 21:30:05 -08:00
  • 5d99e1bfee Initial prep for fixing DSG0 to use RK05. Mostly notes, a few added comments. Josh Dersch 2019-11-08 17:40:35 -08:00
  • 8495481b64 Latest changes. INIT now works; loads MONITOR into memory and executes it. Swapping appears to work. Filesystem routines stubbed out. Josh Dersch 2019-11-08 16:17:21 -08:00
  • e2226765af Adding LCM mods to run TSS/8 entirely off of RK05. Initial checkin. Josh Dersch 2019-11-07 17:04:43 -08:00
  • 116cbe08db added README.md Brad Parker 2016-01-02 12:17:45 -05:00
  • e526fff7c6 added new tss8 source dirs brad 2016-01-02 16:39:18 +00:00
  • c164b2a51d changes for building tss8 variants brad 2016-01-01 21:55:02 +00:00
  • 538ee18f3f fixes for later tss brad 2016-01-01 21:52:21 +00:00
  • ae715df32d brad 2011-11-25 13:03:04 +00:00
  • c6092ebd9a typo brad 2011-11-25 13:00:25 +00:00
  • 8974fd8ff1 synthesis brad 2010-10-26 11:20:13 +00:00
  • 67880416ac brad 2010-10-26 11:18:34 +00:00
  • e2df0883bd brad 2010-10-23 23:31:49 +00:00
  • 74d2f39307 brad 2010-10-23 23:31:38 +00:00
  • 750e709c2a verilator brad 2010-10-23 23:30:54 +00:00
  • afd354d8ad brad 2010-10-23 23:29:39 +00:00
  • ae67233303 new brad 2010-10-23 23:29:25 +00:00
  • 0622c1c3a8 fixed bug in tt tx state machine not asserting interrupt brad 2010-10-23 23:24:52 +00:00
  • 3d425fe732 brad 2010-06-07 20:36:11 +00:00
  • f51c91419b brad 2010-06-07 20:35:46 +00:00
  • c9c88d78f1 brad 2010-06-05 17:10:30 +00:00
  • 6ef3fdd93b brad 2010-06-05 17:09:48 +00:00
  • 57bff22430 debug cleanups from synthesis brad 2010-06-05 16:36:26 +00:00
  • 093c51e625 brad 2010-06-05 15:58:50 +00:00
  • e1cd575b11 fixed bug; user osr/hlt didn't trap brad 2010-06-05 15:57:39 +00:00
  • b734f58acd tss8 testing brad 2010-06-02 15:21:04 +00:00
  • 44fd080f1d added rf behavioral model brad 2010-06-02 15:19:36 +00:00
  • ee7e45a41d fixed clock timing for sim brad 2010-06-02 15:18:24 +00:00
  • ff5900bdef fixed rf emulation bugs brad 2010-06-02 13:24:36 +00:00
  • 0c02cdd19d debugging kw8i user brad 2010-05-24 21:33:24 +00:00
  • 2d61ca13fb cleaned up tt/uart interaction; fixed double input on fpga brad 2010-05-23 13:17:26 +00:00
  • 1ef9bc7815 brad 2010-04-24 10:37:33 +00:00
  • 9bbe1a147e brad 2010-04-24 10:35:11 +00:00
  • e379c07159 fixed bugs so test_top.v works brad 2010-04-24 10:28:53 +00:00
  • 78343d5643 fixed several bugs for fpga version added sim_time check in reset code fixed uart runs hello uart test on fpga brad 2010-04-24 10:27:54 +00:00
  • 1ff40e5627 brad 2010-04-24 01:58:12 +00:00
  • d7e30422b3 brad 2010-04-23 19:59:24 +00:00
  • 53474c6c70 bootrom brad 2010-04-23 19:41:18 +00:00
  • 9aaa93570d added bootrom brad 2010-04-16 13:48:04 +00:00
  • 93f1d3c9d4 changes for hw brad 2010-04-16 13:46:48 +00:00
  • 84def5b611 minor clean up for synthesis brad 2010-04-16 12:31:06 +00:00
  • e421d1a9f1 brad 2010-04-16 12:26:40 +00:00
  • 4e2201fcf8 revamped clocking of internal state brad 2010-04-16 11:12:32 +00:00
  • f30156e5bc brad 2010-04-16 11:11:51 +00:00
  • 2c99f8c26c brad 2010-04-16 01:31:25 +00:00
  • 14330d70c0 brad 2010-04-16 01:30:43 +00:00
  • 2969d31d34 fixed MEX field setting brad 2010-04-16 01:30:13 +00:00
  • c6008db64b brad 2010-04-15 23:39:25 +00:00
  • 8be9d3cd42 brad 2010-04-14 23:41:52 +00:00
  • 6a67dce53a brought rs232 to top brad 2010-04-14 23:41:35 +00:00
  • 6379274142 brad 2010-04-14 23:40:35 +00:00
  • c5c41bb132 using top s3 ram brad 2010-04-14 13:26:17 +00:00
  • fc6b7ec578 using top s3 ram brad 2010-04-14 13:25:35 +00:00
  • 2cb8c22e68 cleanups from first synthesis brad 2010-04-13 17:13:52 +00:00
  • 536430735f first synthesis brad 2010-04-13 17:12:31 +00:00
  • b75bd59721 fixed eol-style brad 2010-04-13 16:38:40 +00:00
  • a04447387a added pli code brad 2010-04-13 14:02:34 +00:00
  • e91720db24 brad 2010-04-13 14:01:42 +00:00
  • 9d89453b0f added ushow for sim output brad 2010-04-13 13:59:00 +00:00
  • e5953e3cb9 debugged rf read side brad 2010-04-13 13:56:55 +00:00
  • 2cb8489480 got tss/8 prompt brad 2010-04-13 13:54:47 +00:00
  • c0e1eef286 added fake uart brad 2010-04-12 12:48:57 +00:00
  • b9cbe40605 brad 2010-04-11 19:07:07 +00:00
  • 951b71c990 clean compile brad 2010-04-11 19:04:16 +00:00
  • 9d76e4f896 brad 2010-04-11 10:34:23 +00:00
  • aeb707c4c3 brad 2010-04-11 10:33:53 +00:00
  • 6a9a4c0b00 added env args brad 2010-04-11 10:33:27 +00:00
  • fe3f5bd3ca debugging - added ide to top brad 2010-04-11 10:31:43 +00:00
  • 8a2da8d778 debugging brad 2010-04-11 10:30:37 +00:00
  • efc438f11d added rf sector buffer brad 2010-04-10 20:16:06 +00:00
  • 30380f136e Added rf sector buffer brad 2010-04-10 20:15:39 +00:00
  • 8abc1b644c changes for data-break brad 2010-04-10 19:27:21 +00:00