24 Commits

Author	SHA1	Message	Date
Andrew Kay	8dc730df8a	Fix receiver start and end sequence detection	2020-07-10 22:15:53 -05:00
Andrew Kay	28fc1c0cef	Add distortion	2020-07-09 07:50:24 -05:00
Andrew Kay	f2166cd960	Add initial coax_tx	2020-07-08 19:19:19 -05:00
Andrew Kay	095f1a3ba5	Add coax_tx_bit_timer	2020-07-08 16:17:17 -05:00
Andrew Kay	80baf7a9ad	Consistency	2020-07-08 16:10:03 -05:00
Andrew Kay	e2974b2365	Implement read	2020-07-05 18:56:36 -05:00
Andrew Kay	eacb8f0eea	Work in progress	2020-07-05 14:41:33 -05:00
Andrew Kay	2bf4c85126	More work in progress	2020-07-05 13:46:45 -05:00
Andrew Kay	90ddeb54d6	Work in progress	2020-07-05 13:00:46 -05:00
Andrew Kay	ed4ca3024d	some progress...	2020-07-04 16:57:46 -05:00
Andrew Kay	293609fc6c	wip	2020-06-23 20:27:12 -05:00
Andrew Kay	d3ca7a1d45	testing rx_coax_bit_timer on TinyFPGA	2020-06-21 18:52:21 -05:00
Andrew Kay	9dd8d37ef5	wip	2020-06-16 16:53:53 -05:00
Andrew Kay	0a03fde6f9	Initial coax_rx_bit_timer	2020-06-15 21:22:30 -05:00
Andrew Kay	03af715ec5	Start over	2020-06-14 10:05:02 -05:00
Andrew Kay	49abcf7e2b	Add data, data_available and data_read	2020-02-18 07:55:13 -06:00
Andrew Kay	811a048685	Initial attempt at receiver	2020-02-17 20:47:46 -06:00
Andrew Kay	2b81a4a961	Clean up bit timer	2020-02-15 09:41:37 -06:00
Andrew Kay	81c6172e7b	Bit timer module	2020-02-14 20:13:01 -06:00
Andrew Kay	d4eaeecec2	Hello world	2020-02-12 23:13:21 -06:00
Andrew Kay	c859688931	Initial attempts at multiple word transmission	2020-02-12 19:44:43 -06:00
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	77821b3f11	Data	2020-02-08 20:03:13 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00