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147 Commits 11 Branches 9 Tags
Commit Graph

29 Commits

Author SHA1 Message Date
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
f754fffdac Make default target runnable 2019-07-29 08:41:03 +02:00
Olof Kindgren
fe9d2677ba Add SERV_CLEAR_RAM parameter 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00
Olof Kindgren
bba836ad8c Fix width mismatches to make code verilator clean 2019-03-25 20:57:13 +01:00
Olof Kindgren
6e91409990 Optimize alu eq check 2019-03-20 08:35:43 +01:00
Olof Kindgren
fe33d6abdc Move dbus address handling to global bufreg 2019-01-15 08:00:32 +01:00
Olof Kindgren
1d04ed9c50 Fix errors in core file 2018-12-16 08:48:48 +01:00
Olof Kindgren
836a013462 Fix clock generation 2018-12-06 22:12:03 +01:00
Olof Kindgren
fc82862e96 Add icepll generator and run tinyfpga BX at 32MHz 2018-12-03 12:26:17 +01:00
Olof Kindgren
25791b10c2 Add memsize param to FPGA targets 2018-11-26 23:13:50 +01:00
Olof Kindgren
ec8252ea0a Add memsize parameter 2018-11-26 17:54:10 +01:00
Olof Kindgren
12039dec0e Add support for setting memory contents during synthesis 2018-11-26 09:49:08 +01:00
Olof Kindgren
e1f5bcc4f3 Rewrite register file 2018-11-26 00:09:52 +01:00
Olof Kindgren
f2e1e4a52b Add support for IceBreaker board 2018-11-22 13:03:23 +01:00
Olof Kindgren
47b2db20c3 Remove missing file from .core 2018-11-21 13:33:54 +01:00
Olof Kindgren
079d973969 Cleanup 2018-11-21 13:22:55 +01:00
Olof Kindgren
9df2a0060b Use custom interconnect. Runs on hw 2018-11-21 13:15:33 +01:00
Olof Kindgren
6e034361d4 Add UART decoder 2018-11-19 09:42:42 +01:00
Olof Kindgren
ff63519607 Temporary hack to blink LED on tinyfpga BX 2018-11-18 21:42:42 +01:00
Olof Kindgren
7666ac4092 synthesized netlist works 2018-11-18 13:05:38 +01:00
Olof Kindgren
a92c933af1 csr, verilator, traps 2018-11-14 12:16:20 +01:00
Olof Kindgren
3c98d35766 Change to wb interface 2018-11-09 21:26:13 +01:00
Olof Kindgren
c90920d9b2 bge, bltu, bgeu 2018-11-01 09:35:49 +01:00
Olof Kindgren
96b1906676 bne, srai 2018-10-30 22:41:05 +01:00
Olof Kindgren
66000a77f5 beq, sw 2018-10-28 23:54:04 +01:00
Olof Kindgren
c2030a95fd jal, addi, lui, lb 2018-10-26 22:52:39 +02:00
Olof Kindgren
e10c41be8d Initial commit 2018-10-23 23:45:41 +02:00