Romain Dolbeau 3af873fdb7 add remove functions, doesn't help

2021-11-07 08:52:56 +01:00

..

engine_code

option to disable upper lane in AES/GCM isntructions; disable them in the code

2021-09-05 09:56:14 -04:00

blit_font.h

Font for the on-screen debug display

2021-10-30 10:04:12 +02:00

blit.c

Add FSR to Vex, use it for unaligned blits

2021-11-01 14:34:34 +01:00

blit.lds

proto CG6

2021-10-15 22:38:27 +02:00

blit.sh

minor changes

2021-10-31 19:58:19 +01:00

cg3_fb.py

support more Po2 FB sizes

2021-10-30 12:51:02 +02:00

cg3_init.fth

CG3 is usable as console and with X11, despite the ugly colors

2021-10-08 20:37:32 +02:00

cg3.fth

add remove functions, doesn't help

2021-11-07 08:52:56 +01:00

cg6_accel.py

minor changes

2021-10-31 19:58:19 +01:00

cg6_fb.py

trying to improve the cg accel stuff

2021-10-24 20:02:34 +02:00

cg6_init.fth

proto CG6

2021-10-15 22:38:27 +02:00

cg6.fth

add remove functions, doesn't help

2021-11-07 08:52:56 +01:00

engine.py

apply patch from betrusted-io/gateware commit 817e284a3d92037b8cb0686735578d2bb60853e9

2021-09-07 05:11:28 -04:00

fbc_init.fth

proto CG6

2021-10-15 22:38:27 +02:00

forth_to_migen_rom.sh

version-specific proms

2021-09-20 12:45:07 -04:00

neorv32_trng_patched.vhd

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

prom_migen.bth

prom

2021-07-14 05:14:19 -04:00

prom_migen.fth

more V1.0 to V1.2 update stuff

2021-09-19 10:18:00 -04:00

prom_V1_0.bth

version-specific proms

2021-09-20 12:45:07 -04:00

prom_V1_2.bth

version-specific proms

2021-09-20 12:45:07 -04:00

sbus_to_fpga_blk_dma.py

fix checksum-less building

2021-11-06 10:18:23 +01:00

sbus_to_fpga_export.py

CG3 is usable as console and with X11, despite the ugly colors

2021-10-08 20:37:32 +02:00

sbus_to_fpga_fsm.py

minor changes

2021-10-31 19:58:19 +01:00

sbus_to_fpga_fsmstat.py

fix broken timeout, some (disabled, for testing) stat stuff

2021-10-30 10:02:33 +02:00

sbus_to_fpga_prom.py

proto CG6

2021-10-15 22:38:27 +02:00

sbus_to_fpga_soc.py

cleanup

2021-11-07 08:52:16 +01:00

sbus_to_fpga_trng.py

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

sbus_wb.py

move the wishbone CDC locally ; speedgrade from part

2021-10-30 10:01:26 +02:00

sbusfpga_stat_ctl.c

ioctl on/off switch on stats + ctrl pgm

2021-08-23 04:48:05 -04:00

sdram_csr.fth

init sdram in PROM

2021-10-07 19:43:07 +02:00

sdram_init.fth

init sdram in PROM

2021-10-07 19:43:07 +02:00

VexRiscv_FbAccel.v

Add sext.b to Vex, as some are generated in -O2/-O3 (none in -Os)

2021-11-01 15:23:27 +01:00

wb_async_reg.v

move the wishbone CDC locally ; speedgrade from part

2021-10-30 10:01:26 +02:00

ztex213_sbus.py

move the wishbone CDC locally ; speedgrade from part

2021-10-30 10:01:26 +02:00