- RlinkCommand,RlinkCommandList: add move version of methods
- use constructor delegation
- use nullptr
- drop empty destructors for pod-only classes
- RlinkCommand: rename IsBlockExt -> HasBlockExt
- RlinkConnect: add BadPort(); used on all hard port checks
- remove contraproductive moves (-Wpessimizing-move)
- add casts (-Wfloat-conversion, -Wdouble-promotion)
- virtual dtor now outlined to streamline vtable
- make Dump non virtual in some cases (-Wnon-virtual-dtor)
- rename variables in shadow situations (-Wshadow)
- use std::function instead of boost
- use c++11 lambda instead of boost::bind in most cases
- use std::bind in few cases where this deems more readable
- use move semantics for passing of function objects
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
- new reference system
- switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
- C++ and Tcl based backend server now fully functional, supports with
DL11, RK11, LP11 and PC11 all devices available in w11a designs
- the old perl based backend server (pi_rri) is obsolete and removed
- operating system kits reorganized
- new C++ and Tcl based backend server supports now RK11 handling
- w11a systems operate with rlink over USB on nexsy2 and nexsy3 boards.
See w11a_os_guide.txt for details
- C++ and Tcl based backend server: many support classes for interfacing to
w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler.
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
