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234 Commits 1 Branch 40 Tags
dd7cdfeceb557c098fb749ee5d21d439fad0ff1f
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18 Commits

Author SHA1 Message Date
wfjm
cb7b906089 Add memory tester for Arty and MIG 
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
 2019-01-03 09:15:07 +01:00
wfjm
f50a85e646 add sys_tst_mig_arty system: a MIG tester 2019-01-01 22:41:44 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
233730885d comment&code cosmetics; minor changes 2018-12-08 09:25:25 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
62eb016ec2 add missing file; minor updates 2017-07-01 13:42:40 +02:00
wfjm
05c7d937c7 Add Digilent Cmod A7 (35 die size) support 
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
- is61wv5128bll: simple memory model (incl tb)
- sn_humanio_emu_rbus: human IO emulator
- 92-retro-usb-persistent.rules: add more board rules
- associated changes
  - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses
  - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
  - ti_rri: adopt Digilent autodetect for CmodA7
- add systems
  - tst_rlink: rlink tested
  - tst_sram: SRAM tester
  - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
 2017-06-28 22:29:09 +02:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00
wfjm
c2c192abe9 comment changes 2017-06-11 20:39:43 +02:00
wfjm
211e1f3ff3 get vivado 2017.1 ready 
- xviv_msg_filter: add version-range tag support
- *.vmfset:
  - drop the nonsense 'Synth 8-6014' messages
  - adopt to different path used by 'Synth 8-3332' messages
 2017-06-10 11:36:32 +02:00
Walter F.J. Mueller
3d3035eb96 correct spelling 2017-04-30 15:33:23 +02:00
Walter F.J. Mueller
bd4b68ca5a add sysmon_stim definition for tb_tst_sram_n4 2017-02-04 16:56:08 +01:00
Walter F.J. Mueller
38470145a0 add sysmon_rbus to sys_tst_sram_n4 (xadc access) 2017-01-14 21:08:57 +01:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support 
- new test bench driver tbrun, give automatized test bench execution
 2016-10-15 07:42:21 +00:00