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wfjm.w11/rtl/vlib/xlib
History
wfjm 14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
2018-12-31 10:00:14 +01:00
..
dcm_sfs_gsim.vbom
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
dcm_sfs_gsim.vhd
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
dcm_sfs_unisim_s3.vbom
- interim release w11a_V0.55 (untagged)
2011-12-23 10:38:59 +00:00
dcm_sfs_unisim_s3.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
dcm_sfs_unisim_s3e.vbom
- interim release w11a_V0.532 (untagged)
2011-11-20 12:31:43 +00:00
dcm_sfs_unisim_s3e.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
gsr_pulse_dummy.vbom
- upgraded CRAM controller, now with 'page mode' support
2016-10-15 07:42:21 +00:00
gsr_pulse_dummy.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
gsr_pulse.vbom
- upgraded CRAM controller, now with 'page mode' support
2016-10-15 07:42:21 +00:00
gsr_pulse.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_keeper_gen.vbom
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
iob_keeper_gen.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_reg_i_gen.vbom
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
iob_reg_i_gen.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_reg_i.vbom
initial source upload (no docs yet)
2010-07-09 18:14:38 +00:00
iob_reg_i.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_reg_io_gen.vbom
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
iob_reg_io_gen.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_reg_o_gen.vbom
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
iob_reg_o_gen.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
iob_reg_o.vbom
initial source upload (no docs yet)
2010-07-09 18:14:38 +00:00
iob_reg_o.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
Makefile
comment&code cosmetics; minor changes
2018-11-11 09:50:46 +01:00
Makefile.ise
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
s6_cmt_sfs_gsim.vbom
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
s6_cmt_sfs_gsim.vhd
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
s6_cmt_sfs_unisim.vbom
- interim release w11a_V0.581 (untagged)
2014-05-29 21:30:01 +00:00
s6_cmt_sfs_unisim.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
s7_cmt_sfs_2_gsim.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
s7_cmt_sfs_2_gsim.vhd
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
s7_cmt_sfs_2_unisim.vbom
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
s7_cmt_sfs_2_unisim.vhd
Add basic DDR memory support
2018-12-31 10:00:14 +01:00
s7_cmt_sfs_gsim.vbom
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
s7_cmt_sfs_gsim.vhd
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
s7_cmt_sfs_unisim.vbom
- added support for Vivado
2015-03-09 19:26:25 +00:00
s7_cmt_sfs_unisim.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
sfs_gsim_core.vbom
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
sfs_gsim_core.vhd
reorganize dcm/mmcm/ppl sim models
2018-11-09 17:48:56 +01:00
usr_access_unisim.vbom
- Code base cleaned-up for vivado, fsm now inferred
2016-06-26 16:02:42 +00:00
usr_access_unisim.vhd
get disclaimers in line with GPL V3 License.txt
2018-01-02 21:57:40 +01:00
xlib.vhd
Add basic DDR memory support
2018-12-31 10:00:14 +01:00