Miodrag Milanovic
2db8aa1e8a
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
31bceb02e9
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
025af8b6d2
clangformat
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e963ac28bb
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
c0e1f45dc0
Optimize
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
8d3e43d89f
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
65678b876e
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
aeb0ba4e54
Cleanups
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
316ebbf26b
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9f9b5f0e8f
Cleanups
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
23ca3cd2b3
Small fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
96b029d560
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9bf85f6e37
Use CP_OUT for adders
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
6cfccc502f
Fix GUI
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
f57c9f4cb7
Renamed some timings
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9de539cd95
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
d5bde28a7c
Add dummy L2T4
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
5cf5ad9c64
Fix ramio
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
271c9f5b97
Use L2T4 for constant drivers
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
b75b0cc562
Fix ADDF
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
fb4f63f8c2
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
6f8d1f2dba
Fixes for ram_o
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9f1d9d3577
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e32f3a3792
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
d974683ffb
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
3eda1edec8
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e1cc5d06cb
Start using FFs
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
bee4aa0e55
CPE mapping improvements
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
bf7eb65dea
Add lut tree tests for future improvements
2025-06-30 11:22:44 +02:00
YRabbit
39f020b033
Gowin. Unbreak the segment routing. ( #1508 )
...
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.
Also do not allow clock wires for segments.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-06-30 10:14:21 +02:00
Lofty
e642e21f9b
himbaechel: output normalised wire in getWireByName ( #1506 )
2025-06-25 18:46:19 +02:00
gatecat
9ade2d1877
himbaechel: Add Python binding for get_tile_wire_range
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 18:37:17 +02:00
gatecat
1cd1e4a8d9
xilinx: Fix packing of weird mux trees
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 12:38:11 +02:00
gatecat
23cf1d3b92
docs: Fix outdated content in generic.md
...
Fixes #1263
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 12:02:27 +02:00
gatecat
ff695f26d5
sdc: Fix EOF handling during string parse
...
Fixes #1490
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:58:11 +02:00
gatecat
f74aee7047
gowin: Remove logspam during build
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:49:45 +02:00
gatecat
a77eb9e941
ice40: Fix accidental division by DIVR in 2_PAD mode
...
Fixes #1500
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:44:16 +02:00
Frans Skarman
0c86a218fd
Add sources to detailed timing report ( #1502 )
2025-06-25 11:39:25 +02:00
YRabbit
66f051d853
Gowin. BUGFIX. Stupid == vs = ( #1504 )
...
he good thing is that these cases are very few.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-06-24 13:24:10 +02:00
Miodrag Milanovic
311a1a711d
gatemate: do not use special serdes pins for auto placement
2025-06-18 09:56:54 +02:00
Miodrag Milanovic
f58dd2d719
clangformat
2025-06-18 09:12:14 +02:00
Miodrag Milanović
7318d6a8ba
gatemate: Multi die support and primitives model improvement ( #1501 )
...
* SER_CLK support
* Update constids
* wip
* CLK_FEEDBACK
* Handle SER_CLK and SER_CLK_N
* clangformat
* Cleanup
* Use _ as separator for PLL CFGs
* Remove unused clocking cells
* Do not use same name for IO models
* Fix IDDR merge
* Cleanup
* Properly handle user global signals
* Move signal inversion in bitstream creation
* Start adding multi die support
* Display die location for pins used
* Do not use constant s as locations
* Cleanup SB_DRIVE handling
* Use DDR locations from chip database
* Place only in prefered die for now
* Set D2D
* Fixed typos
2025-06-18 08:32:57 +02:00
Lofty
5275c14ac0
gatemate: include DDR route-throughs in clock router ( #1499 )
...
* route_clock: small cleanup
* gatemate: include DDR route-throughs for clock router
2025-06-10 18:00:15 +02:00
YRabbit
000faab213
Gowin. BUGFIX. Fix routing of the FF inputs. ( #1498 )
...
A segment router replaces the source-to-sink connection by
general-purpose PIPs with bus-branch segment network connections.
The problem arises when the source is connected to the sinks directly
without switching as in the case of LUT->DFF, such wires should be left
as is, which is what this PR does.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-06-10 07:54:20 +02:00
Miodrag Milanovic
fd3b4d36e7
gatemate: fix CLK inversion
2025-06-04 18:53:58 +02:00
Miodrag Milanovic
bac5a9145f
gatemate: memory clock signal handling
2025-05-29 13:26:35 +02:00
Miodrag Milanovic
9994fdb393
gatemate: make sure to use latest chipdb
2025-05-27 15:37:25 +02:00
Miodrag Milanović
12f597dcd1
gatemate: propagate clock constraints on input ports ( #1497 )
2025-05-26 11:16:45 +02:00
Miodrag Milanovic
e7f52d1b6b
gatemate: enable only used banks, including CFG one
2025-05-24 14:56:07 +02:00
Lofty
9cfc7ee263
gatemate: improve estimateDelay ( #1494 )
2025-05-22 09:15:12 +02:00
