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Commit Graph

15 Commits

Author SHA1 Message Date
aap
d8edd19b0d implemented mul and div subroutines 2016-12-10 19:18:16 +01:00
aap
534d4521c3 added quartus project files 2016-12-10 00:00:16 +01:00
aap
69613da23e changed verilog code for synthesis 2016-12-09 23:31:27 +01:00
aap
45bd177a73 verilog character instructions 2016-11-24 16:13:49 +01:00
aap
844810b249 verilog BLT 2016-11-24 11:04:41 +01:00
aap
f926fd9098 BLK 2016-11-23 09:52:46 +01:00
aap
db93c803c8 work on IOT, AR, SH and SC 2016-11-21 11:39:40 +01:00
aap
2268d61557 work on AR and MQ 2016-11-17 21:40:20 +01:00
aap
a1d5d59e04 some more AR stuff 2016-11-17 00:54:09 +01:00
aap
9c3ca3988f basic E cycle working, S done 2016-11-16 17:06:27 +01:00
aap
712c0bddf6 implemented S cycle, started E 2016-11-15 23:57:55 +01:00
aap
dff2d4cff2 verilog instruction decoding 2016-11-14 23:44:16 +01:00
aap
a2f609fe66 implemented I and A cycles in verilog 2016-11-14 07:01:05 +01:00
aap
14a82a7e61 rewrote the verilog code 2016-11-13 02:06:34 +01:00
aap
fb47930b1b started to write a verilog simulation 2016-11-09 19:24:07 +01:00