make check has stopped working recently:
java.lang.ClassCastException: java.lang.Class cannot be cast to firrtl.options.Dependency
at scala.collection.LinearSeqOptimized.foldLeft(LinearSeqOptimized.scala:126)
at scala.collection.LinearSeqOptimized.foldLeft$(LinearSeqOptimized.scala:122)
at scala.collection.immutable.List.foldLeft(List.scala:89)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$_targets(DependencyManager.scala:34)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$_targets$(DependencyManager.scala:33)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$_targets$lzycompute(DependencyManager.scala:414)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$_targets(DependencyManager.scala:414)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$prerequisiteGraph(DependencyManager.scala:115)
at firrtl.options.DependencyManager.firrtl$options$DependencyManager$$prerequisiteGraph$(DependencyManager.scala:113)
at firrtl.options.PhaseManager.firrtl$options$DependencyManager$$prerequisiteGraph$lzycompute(DependencyManager.scala:414)
I need to investigate, but setting chisel3 to 3.2.5 fixes it for now.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Added a couple of improvements to the Makefile and Readme:
* Restructured the Makefile to support multiple boards based on variable
* Verilator build is also done in Docker container with local option
* Restructured Readme to reflect changes in the Makefile
* Support for running the verilator chiselwatt binary in a Docker
container in case the OS is not Linux.
Signed-off-by: Carlos de Paula <me@carlosedp.com>
For simplicity we originally made loads and stores slow instructions. We
now want to integrate them into the fast pipeline, so add a new cycle to
the pipeline (called memory).
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This adds support for the cheap Colorlight 5A-75B ECP5 based board.
UART RX is on J19, labelled key+ on the silk screen on the back
UART TX is on J1, pin 1.
All the I/Os on this board go through bidirectional level shifters that
appear to be hardwired as outputs. To get an input pin for UART RX, we
use the button I/O which is also routed to connector J19. The downside is
we can't use the button for reset.
One potential issue is that UART TX is 5V but UART RX is 3.3V. To keep
the FPGA happy any attached UART chip needs to output 3.3V, but it also
needs to be 5V tolerant to handle the level shifted input.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Break the writeback mux into two chunks so that all units that have RC
instructions mux into an intermediate signal wrRcData. This gets fed into
the compare logic.
Compare instructions are all fed through the Adder, so use the adder
output instead of the writeback mux.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
We need to clean up the nia/fetch handling, but avoid the situation
where we come out of reset right around the time completed goes high.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
