antonblanchard.microwatt

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efd0571b5f Merge pull request #461 from paulusmack/master master Paul Mackerras 2026-02-05 10:05:42 +11:00
81792f599b arty a7: Connect SD card interface to microSD socket on LCD touchscreen board Paul Mackerras 2021-12-31 18:09:54 +11:00
185008c907 Merge pull request #460 from paulusmack/fixes Paul Mackerras 2026-02-04 11:43:06 +11:00
c7531e592c arty a7: Add facilities to get A/D conversions from the touchscreen Paul Mackerras 2021-12-18 16:27:11 +11:00
172eae61cb arty a7: Add an interface for a TFT LCD touchscreen Paul Mackerras 2021-12-15 19:59:15 +11:00
7f4e0185b5 xilinx_mult: Eliminate a Vivado warning Paul Mackerras 2026-01-27 15:44:44 +11:00
d4fec95044 arty a7: Turn on LED 5 when SD card command-done interrupt is enabled Paul Mackerras 2026-01-28 10:27:24 +11:00
dcd1072c25 arty a7: Put the top 8 GPIOs on pmod B Paul Mackerras 2024-01-13 20:46:55 +11:00
6100e7b50e dcache: Fix another dcache bug causing occasional load data corruption Paul Mackerras 2026-02-04 08:48:34 +11:00
a1d83ba91a tests/mmu: Add a test for a faulting load near the end of a page Paul Mackerras 2026-01-31 16:08:22 +11:00
41e341f260 icache: Clear fetch failed flag on flush Paul Mackerras 2026-01-31 16:06:20 +11:00
16c3eda1b1 arty a7: Rework status LED colours Paul Mackerras 2026-01-14 14:43:35 +11:00
90df07b950 arty a7: Add connection to i2c RTC chip on port JD Paul Mackerras 2023-09-12 08:51:36 +10:00
4f06a01731 arty a7: Add a second SD card interface on pmod JC Paul Mackerras 2025-12-31 08:43:44 +11:00
6366fbb5a7 arty a7: Simplify GPIO connections Paul Mackerras 2026-01-26 16:42:21 +11:00
8339795d0c Merge pull request #459 from paulusmack/fixes Paul Mackerras 2026-01-26 16:20:10 +11:00
6eaf22ea95 dcache: Fix stalls that occurred occasionally with dcbt followed by ld Paul Mackerras 2026-01-17 22:47:14 +11:00
fdd98d88d4 FPU: Fix zero result detection in fmadd-family instructions Paul Mackerras 2026-01-14 08:57:07 +11:00
d02e8e6f93 Merge pull request #458 from paulusmack/fixes Paul Mackerras 2026-01-10 22:17:50 +11:00
84eebf5c7c execute1: Fix bug causing SRR0 to be set to 4 more than the correct value Paul Mackerras 2026-01-02 17:29:33 +11:00
aadd22267f execute1: Don't increment the LOG_ADDR SPR after reading it Paul Mackerras 2026-01-02 17:25:27 +11:00
a7420c2a4d dcache: Fix bug causing load to return incorrect data Paul Mackerras 2025-12-27 15:22:09 +11:00
c78d9b32ef loadstore1: Ensure tlbie instructions get completed Paul Mackerras 2025-12-23 12:07:02 +11:00
f9dc3ecdc8 execute1: Correct FSCR[IC] value for prefix unavailable interrupt Paul Mackerras 2025-12-20 17:29:45 +11:00
a1624a50da Merge pull request #457 from paulusmack/fixes Paul Mackerras 2025-12-30 18:10:19 +11:00
09b340e845 FPU: Update committed FPSCR value correctly Paul Mackerras 2025-12-04 08:48:27 +11:00
1ad8848655 FPU: Improve zero result detection and simplify final states Paul Mackerras 2025-12-14 08:42:23 +11:00
f8a11420ca FPU: Check for rounding overflow in 32-bit convert-to-integer operations Paul Mackerras 2025-12-13 11:31:31 +11:00
6fe4b549f5 FPU: Improve accuracy in multiply-add almost-cancellation cases Paul Mackerras 2025-12-12 18:51:13 +11:00
80c81b58ef FPU: Generate correct result sign when B is denormal Paul Mackerras 2025-12-12 16:44:43 +11:00
f631dcd700 FPU: Set FPRF correctly on multiply result that underflows Paul Mackerras 2025-12-12 12:44:13 +11:00
b122577a4e FPU: Be more careful about preserving low-order bits in multiply-add instrs Paul Mackerras 2025-12-12 10:12:10 +11:00
59992eab90 FPU: Avoid doing overflow processing twice in OE=1 case Paul Mackerras 2025-12-11 13:15:00 +11:00
9f27f60b26 FPU: Clear FPSCR[FR,FI] on overflow in convert-to-integer instructions Paul Mackerras 2025-12-11 09:19:12 +11:00
37edba4da7 FPU: Normalize B operand for multiply-add instructions Paul Mackerras 2025-12-11 09:01:41 +11:00
d33f31509b FPU: Clear S in ADD_SHIFT state Paul Mackerras 2025-12-10 21:02:06 +11:00
b8f7cbd894 FPU: Record bits shifted out of addend in fmadd-family instructions Paul Mackerras 2025-12-10 20:14:35 +11:00
009ee1c9c5 FPU: Renormalize frsp operand if denormalized Paul Mackerras 2025-12-10 11:47:32 +11:00
baf8f5f8c6 FPU: Force reserved FPSCR bit 11 to zero Paul Mackerras 2025-12-10 11:02:23 +11:00
a18c462b27 FPU: Ignore stale P contents in short-circuit multiply-add Paul Mackerras 2025-12-10 09:34:20 +11:00
41988e3b5f FPU: Fix comparison of remainder in square root code Paul Mackerras 2025-12-10 08:37:02 +11:00
f3b9566ae2 FPU: Round to single precision for fcfid[u]s Paul Mackerras 2025-12-09 19:38:59 +11:00
e5651e2eab FPU: Avoid adding bias twice in UE=1 underflow case Paul Mackerras 2025-12-09 16:12:05 +11:00
a0755935f4 FPU: Normalize B for fmadd family instructions Paul Mackerras 2025-12-09 11:35:12 +11:00
32919435a3 FPU: Allow mtfsb* to set FPSCR[FX] implicitly Paul Mackerras 2025-12-09 11:20:23 +11:00
e471581222 FPU: Do result processing on denorm short-circuit results when FPSCR[UE] is set Paul Mackerras 2025-12-08 19:12:03 +11:00
0478fe41dd FPU: Reset FPSCR[FR,FI] at beginning of fcfid* Paul Mackerras 2025-12-08 15:03:43 +11:00
f252dba43d FPU: Only apply zero subtraction result sign rule when result is exactly zero Paul Mackerras 2025-12-08 14:15:24 +11:00
8a204f1058 FPU: Set FPSCR exception summary based on individual invalid exception bits Paul Mackerras 2025-12-08 08:07:28 +11:00
fb71f62b83 FPU: Round finite special-case results to single precision if required Paul Mackerras 2025-12-06 20:53:38 +11:00
de71a6119c FPU: Make FPSCR bit 11 always read as 0 Paul Mackerras 2025-12-06 18:23:27 +11:00
ca792f3b13 FPU: Make convert-to-integer-word instructions behave like P9 Paul Mackerras 2025-12-06 18:09:20 +11:00
82825a11ba FPU: Set result sign correctly for denorm +/- 0 case Paul Mackerras 2025-12-06 17:55:11 +11:00
37b1afc7f7 FPU: Make fri* instructions set FPSCR[FR,FI] to zero Paul Mackerras 2025-12-06 17:28:31 +11:00
dcd85164c6 FPU: Make fsel not alter FPSCR Paul Mackerras 2025-12-06 17:09:46 +11:00
066e38b8ea FPU: Do proper over/underflow handling for single-precision [fm]add Paul Mackerras 2025-12-06 16:26:52 +11:00
d540171f60 FPU: Ignore Rc bit for mffs* variants other than plain mffs Paul Mackerras 2025-12-06 14:08:48 +11:00
0e11f80f2f FPU: Set FPSCR[FPRF] to zero for convert to integer operations Paul Mackerras 2025-12-06 13:32:56 +11:00
2f29daab2d FPU: Fix setting of r.x for single-precision operations Paul Mackerras 2025-12-06 11:15:11 +11:00
577bbb8f5d tests/fpu: Add test case for denorm input in frsp test Paul Mackerras 2025-11-19 13:36:04 +00:00
ab3783b61b FPU: Fix setting of r.x Paul Mackerras 2025-11-19 13:32:14 +00:00
7b1febcbd3 tests/fpu: Check setting of FR and FI in FPSCR by frsp instruction Paul Mackerras 2025-11-18 22:49:45 +00:00
e60840eabc FPU: Make sure FR and FI in FPSCR get reset on special-case arith instructions Paul Mackerras 2025-11-18 22:42:37 +00:00
0b3df8ab00 bitsort: Fix bperm instruction (#456) Paul Mackerras 2025-12-15 08:27:42 +11:00
da695e7927 execute1: Fix bug where LPCR[HEIC] disabled interrupts in problem state (#453) Paul Mackerras 2025-10-10 10:31:43 +11:00
fabe9a4feb Merge pull request #452 from paulusmack/master Paul Mackerras 2025-10-04 08:10:47 +10:00
79e69d2a23 execute2: Simplify execute2 logic to improve timing Paul Mackerras 2025-09-29 19:53:43 +10:00
9326fc7f18 tests/modes: Test that mfspr/mtspr to unimplemented SPR in user mode causes HEAI Paul Mackerras 2025-09-25 11:43:24 +10:00
0255283159 tests/spr_read: Test that mfspr/mtspr to SPRs 0,4,5,6 generate HEAI Paul Mackerras 2025-09-24 22:10:48 +10:00
5548a5ba26 execute1: Make mfspr/mtspr to SPRs 0,4,5,6 generate HEAI Paul Mackerras 2025-09-25 22:37:47 +10:00
9c40ddffd2 execute1: Implement LPCR[EVIRT] bit Paul Mackerras 2025-09-25 09:01:19 +10:00
1d758f1d74 execute1: Simplify no-op behaviour of mfspr Paul Mackerras 2025-09-17 09:47:30 +10:00
788f7a1755 core: Improve timing on bypass control paths Paul Mackerras 2025-09-27 08:52:18 +10:00
f2166d326c tests/fpu: Add a test for result writing being suppressed Paul Mackerras 2025-09-20 15:19:33 +10:00
34cf092bf6 control: Fix forwarding when previous result write is suppressed Paul Mackerras 2025-09-22 09:15:11 +10:00
9f9f9046ee tests/spr_read: Add a check for no-op behaviour of mtspr and mfspr Paul Mackerras 2025-09-17 17:57:08 +10:00
4073aa5ffd execute1: Fix setting HEIR and FSCR[IC] on interrupts Paul Mackerras 2025-09-29 16:12:40 +10:00
6fe0b6e444 execute1: Fix no-op behaviour of reading undefined SPRs Paul Mackerras 2025-09-19 11:16:33 +10:00
7619df6b78 core: Implement HRMOR as a read-only zero register (#450) Paul Mackerras 2025-09-03 11:43:11 +10:00
198ad6d199 genesys2: Fix SPI_FLASH_OFFSET (#449) Boris Shingarov 2025-08-17 19:48:23 -04:00
a6858f716a genesys2: Fix DDR3 PHY cmd_latency (#448) Boris Shingarov 2025-08-17 19:46:57 -04:00
152eef1156 Merge pull request #446 from paulusmack/master Paul Mackerras 2025-08-13 20:33:45 +10:00
d2bf3f3580 core: Implement hypervisor doorbell interrupt and msg* instructions Paul Mackerras 2025-08-08 08:55:48 +10:00
ca872faede core: Consolidate several OP_* values into a single OP_COMPUTE Paul Mackerras 2025-06-03 19:36:12 +10:00
a764fd464e Merge pull request #445 from paulusmack/master Paul Mackerras 2025-08-07 08:50:18 +10:00
8f6c727309 execute1: Rework data paths for mfspr and mtspr Paul Mackerras 2025-06-03 14:07:15 +10:00
fc3ff2d340 logical: Use sub_select rather than insn_type to select logical op Paul Mackerras 2025-06-02 22:10:40 +10:00
54173a0677 decode: Move result_sel and subresult_sel into main decode table Paul Mackerras 2025-05-31 21:02:09 +10:00
8bfce4890b predecode: Add some more comments Paul Mackerras 2025-05-31 11:21:14 +10:00
0f8c4afc52 openocd: Update arty config for newer openocd versions Paul Mackerras 2025-05-30 10:08:04 +10:00
0bf1dcedbd acorn-cle-215: Implement SMP and enable FPU and BTC Paul Mackerras 2025-05-30 10:05:41 +10:00
ce5a967ac2 soc: Allow for up to 1GB of DRAM in address decoding Paul Mackerras 2025-05-30 10:03:25 +10:00
4282d37741 FPU: Faster method for testing for 1-bits at right end of R Paul Mackerras 2025-04-20 14:30:28 +10:00
04b0c901e0 dcache: Simplify expression for read enable of cache RAM Paul Mackerras 2025-04-19 18:12:03 +10:00
8605dcb4f1 decode2: Use register addresses from decode1 rather than recomputing them Paul Mackerras 2025-04-19 10:14:28 +10:00
e14712e45c core: Simplify operand presentation for hash instructions Paul Mackerras 2025-04-18 16:05:12 +10:00
dc9d351833 Merge pull request #444 from paulusmack/master Paul Mackerras 2025-04-16 18:06:14 +10:00
de2e8f81ee decode: Execute cpabort as a no-op Paul Mackerras 2025-04-16 11:49:15 +10:00
b65dde1a95 arty a7: Display run status of two CPUs on LEDs 6 and 7 Paul Mackerras 2025-01-10 13:22:56 +11:00
51dd7f578f countbits: Move more popcount calculation before the clock edge Paul Mackerras 2025-04-15 09:59:44 +10:00

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