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Mono Color

• ea0b843662 loadstore1: Better expression for store data formatting Paul Mackerras 2020-07-18 16:37:03 +10:00
• 2cb1d7671e loadstore1: Further tweaks to improve synthesis with yosys/nextpnr Paul Mackerras 2020-07-16 09:26:47 +10:00
• 128fe8ac26 dcache: Ease timing on wishbone data and byte selects Paul Mackerras 2020-07-10 19:04:37 +10:00
• 36297d35f8 decode1: Fix formatting Paul Mackerras 2020-07-15 09:00:44 +10:00
• b80e81e123 loadstore1: Separate address calculation for MMU to ease timing Paul Mackerras 2020-07-13 17:43:52 +10:00
• 91cbeee77c loadstore1: Generate busy signal earlier Paul Mackerras 2020-07-13 12:18:53 +10:00
• c180ed0af0 dcache: Output separate done-without-error and error-done signals Paul Mackerras 2020-07-12 20:05:53 +10:00
• 56420e74f3 dcache: Ease timing on calculation of acks remaining Paul Mackerras 2020-07-11 22:23:31 +10:00
• dc8980d5a5 dcache: Improve timing of valid/done outputs Paul Mackerras 2020-07-11 17:46:03 +10:00
• 893d2bc6a2 core: Don't generate logic for log data when LOG_LENGTH = 0 Paul Mackerras 2020-07-11 15:40:27 +10:00
• 03a3a5d326 countzero: Faster algorithm for count leading/trailing zeroes Paul Mackerras 2020-07-11 12:05:43 +10:00
• 1f2058a0ed MMU: Improve timing of done signal back to loadstore1 Paul Mackerras 2020-07-11 11:00:53 +10:00
• 1be6fbac33 dcache: Remove dependency of r1.wb.adr/dat/sel on req_op Paul Mackerras 2020-07-11 09:10:24 +10:00
• c01e1c7b91 dcache: Update TLB PLRU one cycle later Paul Mackerras 2020-07-10 20:32:35 +10:00
• b2ba024a48 loadstore1: Eliminate two_dwords variable Paul Mackerras 2020-07-10 20:11:15 +10:00
• 9160e29c56 execute1: Ease timing on redirect_nia Paul Mackerras 2020-07-10 19:07:47 +10:00
• 31587affb3 dcache: Do PLRU update one cycle later Paul Mackerras 2020-07-10 17:47:52 +10:00
• 144d8e3c61 icache: Do PLRU update one cycle later Paul Mackerras 2020-07-10 10:04:56 +10:00
• 57ad7effed Merge pull request #232 from gromero/for-anton Michael Neuling 2020-07-14 16:08:04 +10:00
• dee71e8f01 Enhance hello_world Gustavo Romero 2020-07-13 16:54:32 -03:00
• 2081bdaa27 Merge pull request #228 from ozbenh/misc Michael Neuling 2020-07-09 12:25:50 +10:00
• 4d7143bf6b Merge pull request #222 from iamjpn/master Michael Neuling 2020-07-09 11:10:45 +10:00
• 737ebd92f5 tests: Add tests for the PVR Jordan Niethe 2020-07-08 14:34:42 +10:00
• ac81bb17ac litedram: Regenerate Benjamin Herrenschmidt 2020-07-08 17:34:40 +10:00
• 079af6443e litedram: Update generator to work with latest LiteX Benjamin Herrenschmidt 2020-07-08 17:30:10 +10:00
• cc35c49928 litedram: Add generator for Genesys2 Benjamin Herrenschmidt 2020-06-24 13:43:29 +10:00
• bedc9c0085 litedram: l2: Add a few comments about litedram behaviour Benjamin Herrenschmidt 2020-06-26 14:52:06 +10:00
• 02abb135a8 litedram: l2: Add support for more geometries Benjamin Herrenschmidt 2020-06-24 12:02:55 +10:00
• 1441b2a859 litedram: l2: Latency improvements Benjamin Herrenschmidt 2020-06-22 17:27:05 +10:00
• b0241d9f2d corefile/nexys_video: Parameter fixes Benjamin Herrenschmidt 2020-07-08 14:00:27 +10:00
• a5fa92f71b fpga: nexys-video: Wire up core_alt_reset Benjamin Herrenschmidt 2020-06-26 23:34:14 +10:00
• 5449d842dd nexys_video: Fix nexys-video build Benjamin Herrenschmidt 2020-06-25 14:05:03 +10:00
• 3c2739e10a spi: Send dummy clocks at boot Benjamin Herrenschmidt 2020-07-08 16:13:27 +10:00
• bf36ea365b Merge pull request #223 from mikey/ecp5 Paul Mackerras 2020-07-08 10:48:26 +10:00
• b3b28044f8 Create github artifacts for ECP5 devices Michael Neuling 2020-07-07 21:18:34 +10:00
• 5aaa63ee3b Add PLL for ECP5 device Michael Neuling 2020-07-07 21:15:34 +10:00
• 4e977bf8a9 Merge pull request #220 from mikey/ghdl-makefile Anton Blanchard 2020-07-07 20:54:06 +10:00
• 65fc34cf6e Merge pull request #209 from mikey/yosys Anton Blanchard 2020-07-07 20:44:02 +10:00
• 17fc77cef2 core: Implement PVR register Jordan Niethe 2020-07-07 20:37:52 +10:00
• 1697f8a08f Use $(GHDL) rather than ghdl in Makefile Michael Neuling 2020-07-04 11:12:05 +10:00
• 8bfc6a21b9 Add yosys/nextpnr ecp5 and verilog build to CI Michael Neuling 2020-06-22 13:10:13 +10:00
• 10a1a86ba0 Add FPGA_TARGET=ECP5-EVN make option for synthesis build Michael Neuling 2020-06-23 17:05:23 +10:00
• ef0dcf3bc6 Add SYNTH_ECP5_FLAGS option for building Michael Neuling 2020-07-02 14:36:14 +10:00
• 45fd2354f2 Add ram file to synthesis build dependencies Michael Neuling 2020-07-02 15:55:30 +10:00
• 7347786b08 Add uart16550 files to yosys/nextpnr build Michael Neuling 2020-07-02 14:34:43 +10:00
• aae45583d7 Add uart16550 files from fusesoc Michael Neuling 2020-07-02 14:11:16 +10:00
• 3f6d48f2fc Build to tmp file so nextpnr errors don't confuse make Michael Neuling 2020-06-22 13:09:09 +10:00
• 3e0ac8c94c Fix building with yosys/nextpnr Michael Neuling 2020-06-22 13:09:09 +10:00
• 3460afb557 Add yosys builds files to gitignore Michael Neuling 2020-06-22 13:11:03 +10:00
• b1c260599f Send line feed if we get a carriage return in hello world. Michael Neuling 2020-06-23 17:07:12 +10:00
• ce0205b262 Merge pull request #216 from paulusmack/cfar Michael Neuling 2020-06-30 15:47:36 +10:00
• 419c9a68e8 Merge pull request #206 from Jbalkind/icachecleanup Paul Mackerras 2020-06-30 15:01:06 +10:00
• 74062195ca execute1: Do forwarding of the CR result to the next instruction Paul Mackerras 2020-06-19 20:00:16 +10:00
• 0f0573903b execute1: Add latch to redirect path Paul Mackerras 2020-06-19 18:00:37 +10:00
• 9b40b5a77b logical: Only do output inversion for OP_AND, OP_OR and OP_XOR Paul Mackerras 2020-06-19 17:13:06 +10:00
• c2da82764f core: Implement CFAR register Paul Mackerras 2020-06-15 17:45:55 +10:00
• 57604c1a6e Merge pull request #213 from ozbenh/uart16550 Michael Neuling 2020-06-29 12:19:06 +10:00
• 9bbef035a6 Merge pull request #212 from ozbenh/liteeth Michael Neuling 2020-06-29 12:18:44 +10:00
• cc27e239f4 Merge pull request #214 from shingarov/fix-ld-target Michael Neuling 2020-06-29 10:24:49 +10:00
• 49f1389a21 Fix ld error in elf maketarget Boris Shingarov 2020-06-25 05:31:45 -04:00
• 434962bc34 tests: Add updated micropython build with 16550 support Benjamin Herrenschmidt 2020-06-19 21:18:33 +10:00
• fc4e13ae67 sim_console: Fix polling to check for POLLIN Benjamin Herrenschmidt 2020-06-19 20:27:31 +10:00
• fb5c16d05e uart: Make 16550 the default Benjamin Herrenschmidt 2020-06-18 17:14:55 +10:00
• b230677e93 syscon: Add flag to indicate the timebase frequency Benjamin Herrenschmidt 2020-06-23 15:44:37 +10:00
• d654667304 console: Add support for the 16550 UART Benjamin Herrenschmidt 2020-06-18 17:14:41 +10:00
• cc10f6b289 uart: Add a simulation model for the 16550 compatible UART Benjamin Herrenschmidt 2020-06-18 14:00:28 +10:00
• 4eae29801b uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl Benjamin Herrenschmidt 2020-06-18 11:18:30 +10:00
• e3941109af console: Cleanup console API Benjamin Herrenschmidt 2020-06-18 11:06:33 +10:00
• 7575b1e0c2 uart: Import and hook up opencore 16550 compatible UART Benjamin Herrenschmidt 2020-06-16 22:42:15 +10:00
• 76e2c7d81c ex1: Add SPR_TBU support Benjamin Herrenschmidt 2020-06-18 19:41:00 +10:00
• 8366710217 liteeth: Hook up LiteX LiteEth ethernet controller Benjamin Herrenschmidt 2020-06-13 10:04:31 +10:00
• 7566f04fe3 Merge pull request #211 from shenki/spi-constraint Michael Neuling 2020-06-23 16:58:06 +10:00
• 60e5f7b958 spi: Fix dat_i_l constraints Joel Stanley 2020-06-22 18:33:14 +09:30
• 695e081c35 Merge pull request #210 from ozbenh/xics Michael Neuling 2020-06-23 14:32:42 +10:00
• bb54af59de xics: Add support for reduced priority field size Benjamin Herrenschmidt 2020-06-22 23:38:34 +10:00
• 5c2fc47e2c xics: Add simple ICS Benjamin Herrenschmidt 2020-06-17 22:11:58 +10:00
• 8080168327 xics/icp: MFRR starts at 0xff not 0x00 Benjamin Herrenschmidt 2020-06-17 22:07:33 +10:00
• 0b82024b01 tests/xics: Ensure no compiler optimisations in delay() Benjamin Herrenschmidt 2020-06-17 22:06:28 +10:00
• 0fa14f6dec xics: ICP should be big endian ! Benjamin Herrenschmidt 2020-06-17 21:51:16 +10:00
• 311b653d80 tests: Fix Makefile.test to not allow host includes Benjamin Herrenschmidt 2020-06-17 14:00:04 +10:00
• b90a0a2139 Merge pull request #208 from paulusmack/faster Michael Neuling 2020-06-19 11:50:47 +10:00
• 1fedc7a86a Merge pull request #207 from ozbenh/misc Paul Mackerras 2020-06-18 07:26:01 +10:00
• 64efd494e5 fpga: Add a xilinx_specific fileset to microwatt.core Paul Mackerras 2020-06-16 16:59:54 +10:00
• 78de4fef72 Make LOG_LENGTH configurable per FPGA variant Paul Mackerras 2020-06-16 11:37:25 +10:00
• ec2fa61792 execute1: Reduce width of the result mux to help timing Paul Mackerras 2020-06-15 16:59:08 +10:00
• 6687aae4d6 core: Implement a simple branch predictor Paul Mackerras 2020-06-15 15:43:05 +10:00
• 09ae2ce58d decode1: Improve timing for slow SPR decode path Paul Mackerras 2020-06-15 10:02:14 +10:00
• b3799c432b decode1: Add a stash buffer to the output Paul Mackerras 2020-06-15 09:28:03 +10:00
• 67b6117ebf soc: Slight cleanup of IRQ assignments Benjamin Herrenschmidt 2020-06-13 22:29:54 +10:00
• e07b3dd6fa soc: Rename uart_dat8 to uart0_dat8 Benjamin Herrenschmidt 2020-06-13 22:05:39 +10:00
• f9f18906a3 soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding Benjamin Herrenschmidt 2020-06-13 22:04:45 +10:00
• d9bda521aa Minor refactor of icache to make less dependent on wishbone Jonathan Balkind 2020-06-13 18:39:18 -04:00
• a4500c63a2 dcache: Reduce back-to-back store latency from 3 cycles to 2 Paul Mackerras 2020-06-13 23:00:13 +10:00
• bf7def5503 soc: Don't require dram wishbones signals to be wired by toplevel Benjamin Herrenschmidt 2020-06-13 22:19:33 +10:00
• 1ffc89e58b soc: Add defaults for some input signals Benjamin Herrenschmidt 2020-06-13 21:57:01 +10:00
• 4244b54984 soc: Remove unused RESET_LOW generic Benjamin Herrenschmidt 2020-06-13 21:51:31 +10:00
• aebd915f8f mmu: Take an extra cycle to do TLB invalidations Paul Mackerras 2020-06-13 20:27:50 +10:00
• b595963233 dcache: Reduce latencies and improve timing Paul Mackerras 2020-06-11 14:23:50 +10:00
• 65a36cc0fc decode: Work out ispr1/ispr2 in parallel with decode ROM lookup Paul Mackerras 2020-05-12 16:28:42 +10:00
• 209aa9ce3f loadstore1: Reduce busy cycles Paul Mackerras 2020-06-05 14:22:02 +10:00