antonblanchard.microwatt

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2aae3bf7a4 Fix yosys build after MMU merge Anton Blanchard 2020-05-19 11:22:29 +10:00
9287e80711 Merge pull request #174 from antonblanchard/yosys-fixes Anton Blanchard 2020-05-19 10:44:04 +10:00
f96d179f66 Some yosys fixes Anton Blanchard 2020-05-18 10:15:03 +10:00
7c4dab7eb0 Merge pull request #169 from paulusmack/mmu Anton Blanchard 2020-05-19 09:34:41 +10:00
6efb31c924 litedram: Regenerate Benjamin Herrenschmidt 2020-05-15 13:31:11 +10:00
acbdd396a5 soc/core: Add reset latches Benjamin Herrenschmidt 2020-05-15 13:30:01 +10:00
7560e8f2ff arty/nexys: Rework reset with litedram Benjamin Herrenschmidt 2020-05-15 13:20:27 +10:00
3b603402d2 soc_reset: Use counters, add synchronizers Benjamin Herrenschmidt 2020-05-15 13:15:48 +10:00
30fd9aa298 litedram: Forward system reset signal Benjamin Herrenschmidt 2020-05-15 13:11:58 +10:00
c0f537b845 litedram: Remove init delays Benjamin Herrenschmidt 2020-05-15 10:14:53 +10:00
c19b5b8cc7 litedram: Update to new LiteX/LiteDRAM version Benjamin Herrenschmidt 2020-05-12 20:27:15 +10:00
eca0fb5bf1 dcache: Fix bug in store hit after dcbz case Paul Mackerras 2020-05-15 22:01:02 +10:00
13e84b0bbb pp_soc_uart: Fix rx synchronizers and ensure stable tx init state Benjamin Herrenschmidt 2020-05-14 14:26:14 +10:00
bd42580a42 pp_fifo: Fix full fifo losing all data on simultaneous push & pop Benjamin Herrenschmidt 2020-05-14 12:30:11 +10:00
803ee9ef35 Makefile: Improve clean a bit Benjamin Herrenschmidt 2020-05-14 10:12:44 +10:00
edbbf9a125 console: Remove putstr() Benjamin Herrenschmidt 2020-05-14 12:03:39 +10:00
7bc118c7db console: Move console files Benjamin Herrenschmidt 2020-05-14 10:08:06 +10:00
a87b86e54f console: Replace putstr with puts Benjamin Herrenschmidt 2020-05-14 12:03:01 +10:00
88b28a7b17 console: Improve putchar(), add puts() Benjamin Herrenschmidt 2020-05-14 10:09:36 +10:00
941499133e soc: Work around compile error with ghdl 0.37-dev Paul Mackerras 2020-05-14 15:43:33 +10:00
c164a2f4ea Merge branch 'mmu' Paul Mackerras 2020-05-14 15:41:51 +10:00
fcec66acf4 Merge pull request #170 from antonblanchard/litedram Anton Blanchard 2020-05-14 15:08:33 +10:00
60d2b8ac1e Add script for writing to flash on arty Joel Stanley 2020-05-06 11:50:17 +09:30
e3013f5754 litedram: Use 32-bit CSR bus Benjamin Herrenschmidt 2020-05-09 11:20:59 +10:00
7f1f6b8525 litedram: Add support for Microwatt-initialized controller Benjamin Herrenschmidt 2020-05-09 01:09:26 +10:00
c5f5f50738 hello_world: Use new headers and frequency from syscon Benjamin Herrenschmidt 2020-05-08 10:42:01 +10:00
12e8b0952d litedram: Improve sdram init boot messages Benjamin Herrenschmidt 2019-09-24 16:19:29 +10:00
33de131384 Add microwatt_soc.h and io.h include file Benjamin Herrenschmidt 2020-05-08 10:27:33 +10:00
025cf5efe8 syscon: Add syscon registers Benjamin Herrenschmidt 2019-09-24 22:24:31 +10:00
2cef3005cd fpga: Hookup nexys-video to litedram Benjamin Herrenschmidt 2019-09-11 10:59:13 +01:00
3ac815823c fpga: Hookup Arty to litedram Benjamin Herrenschmidt 2019-09-10 18:24:06 +01:00
2843c99a71 MMU: Implement reading of the process table Paul Mackerras 2020-04-24 10:58:56 +10:00
f3c6119cf6 tests/mmu: Add a test of PTE refetching on permission error Paul Mackerras 2020-05-07 20:12:46 +10:00
8ff8b2f256 tests/mmu: Add a test for dcbz with translation on Paul Mackerras 2020-05-04 08:57:05 +10:00
a658766fcf Implement slbia as a dTLB/iTLB flush Paul Mackerras 2020-05-07 20:02:21 +10:00
f54a65f8cf Decode tlbiel as tlbie Paul Mackerras 2020-05-02 14:23:14 +10:00
bee0c94fb4 tests/privileged: Update for instruction translation Paul Mackerras 2020-05-07 12:08:43 +10:00
b342312e4e tests: mmu: Add tests for instruction translation Paul Mackerras 2020-04-28 16:00:00 +10:00
01046527ba MMU: Do radix page table walks on iTLB misses Paul Mackerras 2020-04-28 14:54:22 +10:00
3d4712ad43 Add TLB to icache Paul Mackerras 2020-04-27 17:43:19 +10:00
882a5a0dc0 tests: Add a test for the MMU radix page table walks Paul Mackerras 2020-04-23 15:33:36 +10:00
dee3783d79 MMU: Remove software-loaded dTLB mode Paul Mackerras 2020-05-07 10:17:08 +10:00
3eb07dc637 MMU: Refetch PTE on access fault Paul Mackerras 2020-05-06 20:21:01 +10:00
f6a0d7f9da MMU: Implement data segment interrupts Paul Mackerras 2020-04-23 21:54:08 +10:00
4e6fc6811a MMU: Implement radix page table machinery Paul Mackerras 2020-04-23 15:28:22 +10:00
8160f4f821 Add framework for implementing an MMU Paul Mackerras 2020-04-22 11:10:56 +10:00
d47fbf88d1 Implement access permission checks Paul Mackerras 2020-04-20 12:43:06 +10:00
42d0fcc511 Implement data storage interrupts Paul Mackerras 2020-04-07 16:17:37 +10:00
750b3a8e28 dcache: Implement data TLB Paul Mackerras 2020-04-06 17:54:45 +10:00
635e316f9b Pass mtspr/mfspr to MMU-related SPRs down to loadstore1 Paul Mackerras 2020-04-22 16:53:39 +10:00
3340d8aa9f mw_debug: Add support for reading GSPRs and writing memory Paul Mackerras 2020-05-02 13:31:07 +10:00
dd2e71930c debug: Provide a way to examine GPRs, fast SPRs and MSR Paul Mackerras 2020-05-02 13:26:30 +10:00
5d282a950c Improve architectural compliance of mfspr and mtspr Paul Mackerras 2020-05-02 20:08:10 +10:00
517a91ce5e decode1: Implement eieio as a nop Paul Mackerras 2020-05-02 13:45:39 +10:00
8a0a907e2f Implement the extswsli instruction Paul Mackerras 2020-05-02 13:28:19 +10:00
8bb3c8f8b6 soc: Add DRAM address decoding Benjamin Herrenschmidt 2019-09-10 18:05:56 +01:00
6853d22203 core: Add alternate reset address Benjamin Herrenschmidt 2020-05-07 22:09:59 +10:00
982cf166dd litedram: Add basic support for LiteX LiteDRAM Benjamin Herrenschmidt 2019-09-10 18:05:32 +01:00
31b55b2a75 core: Improve core reset Benjamin Herrenschmidt 2020-05-08 11:36:37 +10:00
fa50df56ef mw_debug: Fix core reset Benjamin Herrenschmidt 2020-05-04 22:16:22 +10:00
3687486d36 Update hello_world for 100Mhz clock Benjamin Herrenschmidt 2020-04-30 17:52:11 +10:00
0f97b320f6 Change default frequency to 100Mhz Benjamin Herrenschmidt 2019-09-30 14:07:16 +10:00
f124dc4a40 xics: Add missing fusesoc core file Benjamin Herrenschmidt 2020-05-08 11:40:39 +10:00
8857bd1f58 Add openocd SPI flashing proxies for Arty Joel Stanley 2020-05-06 11:52:12 +09:30
1ba29a407a Merge pull request #166 from paulusmack/master Anton Blanchard 2020-05-07 09:59:19 +10:00
102fbcfe9a execute1: Fix interrupt delivery during slow instructions Paul Mackerras 2020-05-04 15:17:04 +10:00
fe789190e4 wishbone_debug_master: Fix address auto-increment for memory writes Paul Mackerras 2020-05-01 09:00:21 +10:00
102b304db7 Merge remote-tracking branch 'remotes/origin/master' Paul Mackerras 2020-05-06 14:15:22 +10:00
4db1676ef8 dcache: Don't assert on dcbz cache hit Paul Mackerras 2020-05-04 08:31:18 +10:00
4160f2138d Merge pull request #165 from mikey/xics Anton Blanchard 2020-05-06 13:27:17 +10:00
098c3fbb2b Merge pull request #167 from tomtor/patch-1 Anton Blanchard 2020-05-01 19:52:59 +10:00
c818853a1c Update README.md Tom Vijlbrief 2020-05-01 09:39:49 +02:00
cf4dfeca36 Change the default cross compiler prefix to powerpc64le-linux-gnu- Paul Mackerras 2020-04-29 11:37:02 +10:00
a05ee9fc7f Makefile: fix typo Paul Mackerras 2020-04-29 11:11:22 +10:00
10f4be4309 tests: Add a test for privileged instruction interrupts Paul Mackerras 2020-04-29 09:09:23 +10:00
041d6bef60 dcache: Implement the dcbz instruction Paul Mackerras 2020-04-28 18:11:52 +10:00
167e37d667 Plumb insn_type through to loadstore1 Paul Mackerras 2020-04-03 14:50:17 +11:00
74db071067 execute1: Generate privileged instruction interrupts when MSR[PR] = 1 Paul Mackerras 2020-04-28 19:38:58 +10:00
b55c9cc298 execute1: Improve architecture compliance of MSR and related instructions Paul Mackerras 2020-04-28 20:28:20 +10:00
f21f9dd5a0 Merge pull request #164 from mikey/tags Anton Blanchard 2020-04-23 19:50:16 +10:00
b6bd1ba33d Merge pull request #163 from paulusmack/excpath Anton Blanchard 2020-04-23 19:49:24 +10:00
0076f8bf1d XICS test case Michael Neuling 2020-04-23 14:37:29 +10:00
b4f20c20b9 XICS interrupt controller Michael Neuling 2020-04-23 14:36:05 +10:00
e5a30a1358 Wire up sim uart TX interrupt Michael Neuling 2020-04-23 14:28:59 +10:00
fc5f7506f8 Add calls to dis/enable potato uart IRQ Michael Neuling 2020-04-23 14:28:08 +10:00
ff162e42eb Add VHDL TAGS Michael Neuling 2020-04-08 17:35:32 +10:00
dc6b1df653 execute1: Don't execute ld/st instruction when taking interrupt Paul Mackerras 2020-04-22 13:54:38 +10:00
2b11c81b18 Merge pull request #162 from antonblanchard/bin2hex-removal Anton Blanchard 2020-04-16 18:42:42 +10:00
4c2bd76634 Merge pull request #161 from antonblanchard/hello-world-Makefile Anton Blanchard 2020-04-16 18:42:13 +10:00
05f4f68c54 rust_lib_demo: Remove bin2hex.py Anton Blanchard 2020-04-16 17:44:17 +10:00
afbb99cfd4 Merge pull request #160 from antonblanchard/tomtor-rust-2 Anton Blanchard 2020-04-16 17:40:52 +10:00
06b28be577 hello_world: Use Makefile automatic variables Anton Blanchard 2020-04-16 17:38:07 +10:00
90ed7adf58 rust_lib_demo: Use common console code Anton Blanchard 2020-04-16 17:14:18 +10:00
c37a4c16db rust_lib_demo: Update package dependencies to fix a build error Anton Blanchard 2020-04-16 17:08:15 +10:00
ae55f5efbd Add Rust demo Tom Vijlbrief 2020-01-03 10:34:21 +01:00
d511e088d2 Merge pull request #159 from shenki/fusesoc-ram-16k Anton Blanchard 2020-04-16 15:15:07 +10:00
6a3d2d95df Set default RAM to be 16K in microwatt.core Joel Stanley 2020-04-15 16:06:54 +09:30
04b784011a README: hello world needs 16KB of RAM Joel Stanley 2020-04-15 16:02:21 +09:30
97e3d47a13 Merge pull request #158 from paulusmack/excpath Anton Blanchard 2020-04-14 12:47:00 +10:00
e8a55f900f Merge pull request #157 from paulusmack/master Anton Blanchard 2020-04-09 11:47:05 +10:00

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