antonblanchard.microwatt

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24a34899b4 Add files for openocd v0.11 Joel Stanley 2021-02-17 17:09:47 +10:30
f06ffcf9b7 Add a GPIO controller and use it to drive the shield I/O pins on the Arty Paul Mackerras 2021-02-23 21:44:04 +11:00
6523acc743 Merge pull request #274 from mikey/read-sprs Michael Neuling 2021-02-09 10:06:03 +11:00
d26a157cd7 Add a test to read from all SPRs Anton Blanchard 2021-01-04 14:16:06 +11:00
4c21587c4d Fix DAR/DSISR reading before they are written Michael Neuling 2021-02-08 20:17:48 +11:00
6c7689052d Merge pull request #269 from paulusmack/pipeline Michael Neuling 2021-02-08 17:27:16 +11:00
9a6a7e9fe5 Merge pull request #268 from paulusmack/btc Michael Neuling 2021-02-08 16:38:57 +11:00
7652452367 Merge pull request #273 from antonblanchard/wishbone-checking Michael Neuling 2021-02-08 14:34:53 +11:00
c4e3ade4ed Merge pull request #267 from paulusmack/master Michael Neuling 2021-02-08 14:26:53 +11:00
481f3cdfea Add some wishbone checking Anton Blanchard 2021-02-08 12:15:53 +11:00
17fd069640 core: Allow multiple loadstore instructions to be in flight Paul Mackerras 2020-12-28 15:15:30 +11:00
f583d088b7 loadstore: Convert to 3-stage pipeline Paul Mackerras 2020-11-07 20:50:58 +11:00
f636bb7c39 dcache: Fix bugs in pipelined operation Paul Mackerras 2021-01-18 08:55:56 +11:00
acb3d2d745 core: Send FPU interrupts to writeback rather than execute1 Paul Mackerras 2020-12-23 13:57:40 +11:00
29221315e9 core: Send loadstore1 interrupts to writeback rather than execute1 Paul Mackerras 2020-12-23 12:27:22 +11:00
3cd3449b4b core: Move redirect and interrupt delivery logic to writeback Paul Mackerras 2020-12-23 11:13:21 +11:00
4fd8d9509c execute1: Move CR result to data path process Paul Mackerras 2020-11-27 17:41:39 +11:00
d6ac43251a execute1: Move data-path logic out to a separate process Paul Mackerras 2020-11-26 22:10:30 +11:00
ae2afeca5c core: Track CR hazards and bypasses using tags Paul Mackerras 2020-11-12 22:07:33 +11:00
d290d2a9bb core: Restore bypass path from execute1 Paul Mackerras 2020-11-11 09:42:17 +11:00
c0b45e153b core: Track GPR hazards using tags that propagate through the pipelines Paul Mackerras 2020-11-10 20:04:00 +11:00
a1d7b54f76 core: Crack branches that update both CTR and LR Paul Mackerras 2020-11-11 22:10:38 +11:00
4c61a71a62 core: Crack update-form loads into two internal ops Paul Mackerras 2020-11-11 18:11:04 +11:00
0fb207be60 fetch1: Implement a simple branch target cache Paul Mackerras 2020-12-19 09:25:04 +11:00
f7b855dfc3 execute1: Improve timing on comparisons Paul Mackerras 2020-09-28 14:04:08 +10:00
b0510fd1bb core: Reorganize execute1 Paul Mackerras 2020-09-26 19:58:46 +10:00
658feabfd4 core: Make result multiplexing explicit Paul Mackerras 2020-09-26 17:19:57 +10:00
9ea1ab0215 execute1: Move branch adder after register Paul Mackerras 2020-12-16 20:41:08 +11:00
cb1e3f6d70 decode1: Take an extra cycle for predicted branch redirects Paul Mackerras 2020-12-16 19:32:07 +11:00
6427cab46f loadstore1/dcache: Send store data one cycle later Paul Mackerras 2020-10-31 13:48:58 +11:00
d1f35705c0 loadstore1: Improve timing of data path from cache RAM to writeback Paul Mackerras 2020-09-28 14:02:03 +10:00
54f89afab7 loadstore1: Decide on load formatting controls a cycle earlier Paul Mackerras 2020-09-21 11:41:46 +10:00
c0f282b691 decode1: Implement tlbsync as a no-op Paul Mackerras 2020-10-10 14:34:01 +11:00
d6134babc0 decode1: Implement obsolete dst, dstst, dss instructions as no-ops Paul Mackerras 2020-09-22 10:03:30 +10:00
89a67a18d0 decode: Add a facility field to the instruction decode tables Paul Mackerras 2020-12-12 12:38:06 +11:00
ec5730a75a tests: Add tests for lq/stq and lqarx/stqcx. Paul Mackerras 2020-09-14 18:21:27 +10:00
4b2c23703c core: Implement quadword loads and stores Paul Mackerras 2020-09-12 20:35:03 +10:00
784d409999 dcache: Add more commentary, no code change Paul Mackerras 2020-10-30 22:08:54 +11:00
55f7d99376 decode1: Fix decoding of recommended NOP instruction Paul Mackerras 2020-11-26 22:08:47 +11:00
3361c460b8 core_debug: Stop logging 256 cycles after trigger Paul Mackerras 2020-12-16 09:34:56 +11:00
470f1b2140 core_debug: Add an address trigger to stop logging at a given address Paul Mackerras 2020-11-12 15:06:38 +11:00
5535257c71 FPU: Don't use mask generator for rounding Paul Mackerras 2020-09-21 11:37:10 +10:00
45c5236700 FPU: Relax timing around multiplier output Paul Mackerras 2020-09-19 19:01:49 +10:00
f14e731ec6 mw_debug: Display terminated status when stopping Paul Mackerras 2020-09-22 20:33:08 +10:00
6baf3b519f mw_debug: Extend to handle FPRs Paul Mackerras 2020-09-22 20:22:24 +10:00
2be2440734 Arty A7: Document pin connections for on-board headers Paul Mackerras 2021-01-13 19:51:46 +11:00
d5cf4acfdb execute1: Update comments about XER forwarding Paul Mackerras 2021-01-13 19:45:57 +11:00
f3f159c6dc Check in verilog caravel-20210114 Anton Blanchard 2020-12-16 11:01:42 +11:00
4a7844404e Forgot to add DFFRAM Anton Blanchard 2021-01-14 10:33:24 +11:00
6f697e4f5f Update PVR Anton Blanchard 2021-01-14 10:21:33 +11:00
9910d99320 Not sure we need this Anton Blanchard 2020-12-15 15:29:29 +11:00
9ccf9a7f80 Add a script to post process the microwatt verilog for caravel Anton Blanchard 2020-12-17 15:14:54 +11:00
a45c503aea Connect to the caravel logic analyzer Jordan Niethe 2020-12-14 22:14:09 +11:00
ce27cd3e28 Disable debug log Anton Blanchard 2020-12-16 10:58:48 +11:00
5326455c02 No need to set HAS_FPU and LOG_LENGTH in Makefile Anton Blanchard 2020-12-16 10:51:38 +11:00
bf0c08dd87 tie off wb_ext_io_out Anton Blanchard 2020-12-15 09:20:10 +11:00
120e1ce6ec SPI fixes, and remove reset controller and PLL Anton Blanchard 2020-12-12 12:34:53 +11:00
0664747146 Set alt reset vector to the start of flash at 0xf0000000 and make it programmable externally (using carvel LA) Michael Neuling 2020-12-11 16:09:51 +11:00
4685ff6bbb Add mc*.vhdl from: git@github.com:openpowerwtf/uw_fab.git Michael Neuling 2020-12-11 09:13:39 +11:00
185bcba6bb Add a simple test case Anton Blanchard 2020-12-09 22:29:44 +11:00
83faae4a86 Add RAM_512x64 Anton Blanchard 2020-12-09 17:32:29 +11:00
d1f0ac2e0b Disable second uart since we aren't using it Anton Blanchard 2020-12-13 17:34:39 +11:00
17d93d504a Add a toplevel file for caravel Anton Blanchard 2020-12-09 20:41:27 +11:00
9877db9b97 Disable BOOT_CLOCKS in flash controller Anton Blanchard 2020-12-15 09:20:40 +11:00
d852dedfe4 Reduce the core size Anton Blanchard 2020-12-08 19:26:54 +11:00
7fdbb7c850 Cut down hello_world to fit in 4kB Anton Blanchard 2020-12-21 14:04:05 +11:00
1ee4995cd8 Cleanup some 'U' state issues Michael Neuling 2020-12-16 11:42:49 +11:00
55b6f8be52 Work around ghdl/yosys issue with direct mapped TLB Anton Blanchard 2020-12-09 17:34:07 +11:00
0be86c3a32 Update JTAG TAP controller for Microwatt Anton Blanchard 2020-12-08 18:55:08 +11:00
5e8ba5acb0 First pass at an external JTAG port Anton Blanchard 2020-12-08 07:21:50 +11:00
a3b70ab01e Reset cmd_ready_o in spi_txrx Anton Blanchard 2021-01-04 05:44:23 +11:00
5f8279a14a Merge pull request #263 from antonblanchard/reset-pid Paul Mackerras 2021-01-07 14:47:11 +11:00
45b7312e89 Merge pull request #262 from antonblanchard/reset-tb-decr Paul Mackerras 2021-01-07 14:46:42 +11:00
00446a9169 Merge pull request #259 from antonblanchard/dmi-reset Paul Mackerras 2021-01-07 14:46:04 +11:00
3da9642020 Check in verilog caravel-20210105 Anton Blanchard 2020-12-16 11:01:42 +11:00
6e94b047b8 Not sure we need this Anton Blanchard 2020-12-15 15:29:29 +11:00
7ec66d47fe Add a script to post process the microwatt verilog for caravel Anton Blanchard 2020-12-17 15:14:54 +11:00
901cccd7da Connect to the caravel logic analyzer Jordan Niethe 2020-12-14 22:14:09 +11:00
4667af332e Disable debug log Anton Blanchard 2020-12-16 10:58:48 +11:00
a9a8bee920 No need to set HAS_FPU and LOG_LENGTH in Makefile Anton Blanchard 2020-12-16 10:51:38 +11:00
84f24a4773 tie off wb_ext_io_out Anton Blanchard 2020-12-15 09:20:10 +11:00
2e3668f840 SPI fixes, and remove reset controller and PLL Anton Blanchard 2020-12-12 12:34:53 +11:00
c87b883a82 Set alt reset vector to the start of flash at 0xf0000000 and make it programmable externally (using carvel LA) Michael Neuling 2020-12-11 16:09:51 +11:00
b3a52bf931 Add mc*.vhdl from: git@github.com:openpowerwtf/uw_fab.git Michael Neuling 2020-12-11 09:13:39 +11:00
9747879643 Add a simple test case Anton Blanchard 2020-12-09 22:29:44 +11:00
26fa3eda69 Add RAM_512x64 Anton Blanchard 2020-12-09 17:32:29 +11:00
03e213a393 Disable second uart since we aren't using it Anton Blanchard 2020-12-13 17:34:39 +11:00
6bc8b3e7ad Add a toplevel file for caravel Anton Blanchard 2020-12-09 20:41:27 +11:00
776e3b4815 Disable BOOT_CLOCKS in flash controller Anton Blanchard 2020-12-15 09:20:40 +11:00
e8e3e9bd17 Reduce the core size Anton Blanchard 2020-12-08 19:26:54 +11:00
ef2ee09d1f Cut down hello_world to fit in 4kB Anton Blanchard 2020-12-21 14:04:05 +11:00
104e8b8b2a Cleanup some 'U' state issues Michael Neuling 2020-12-16 11:42:49 +11:00
ffcd9c6989 Work around ghdl/yosys issue with direct mapped TLB Anton Blanchard 2020-12-09 17:34:07 +11:00
47dae4e9d4 Update JTAG TAP controller for Microwatt Anton Blanchard 2020-12-08 18:55:08 +11:00
6544dbe94c First pass at an external JTAG port Anton Blanchard 2020-12-08 07:21:50 +11:00
3f1e2b3a4f Merge pull request #265 from antonblanchard/another-spi-rxtx-reset-issu Anton Blanchard 2021-01-05 20:17:37 +11:00
75be7803b2 Merge pull request #264 from antonblanchard/reset-spi-txrx Anton Blanchard 2021-01-05 20:16:50 +11:00
740f013284 Initialize PID register Anton Blanchard 2021-01-03 16:46:28 +11:00
a0eb4eec17 Fix another reset issue in spi_rxtx Anton Blanchard 2021-01-04 06:04:02 +11:00
bf9a446e3f Reset cmd_ready_o in spi_txrx Anton Blanchard 2021-01-04 05:44:23 +11:00

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