antonblanchard.microwatt

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1d09daae03 loadstore1: Complete mfspr/mtspr a cycle later Paul Mackerras 2020-06-05 13:29:34 +10:00
6701e7346b core: Use a busy signal rather than a stall Paul Mackerras 2020-06-04 20:58:32 +10:00
62b24a8dae icache: Improve latencies when reloading cache lines Paul Mackerras 2020-05-29 09:38:05 +10:00
0809bc898b multiply: Use DSP48 slices for multiplication on Xilinx FPGAs Paul Mackerras 2020-05-21 17:50:54 +10:00
9880fc7435 multiply: Move selection of result bits into execute1 Paul Mackerras 2020-05-21 13:42:46 +10:00
f80da65799 core: Double the dcache and icache sizes Paul Mackerras 2020-06-03 11:26:33 +10:00
b5a7dbb78d core: Remove fetch2 pipeline stage Paul Mackerras 2020-05-10 18:18:03 +10:00
49a4d9f67a Add core logging Paul Mackerras 2020-05-14 13:25:48 +10:00
aab84acda8 scripts/mw_debug: Make progress counts display on one line Paul Mackerras 2020-06-13 19:59:17 +10:00
03f9d7a97e tests/xics: Fix assumption that interrupts happen immediately Paul Mackerras 2020-06-11 14:57:30 +10:00
5a00029519 register_file: Report value being written before asserting it's not X Paul Mackerras 2020-06-13 17:22:56 +10:00
12a257f01e Merge pull request #205 from ozbenh/timing Paul Mackerras 2020-06-13 12:36:16 +10:00
bf6cc2a05a Merge pull request #204 from ozbenh/spi Paul Mackerras 2020-06-13 12:27:40 +10:00
176ae5c306 syscon: Remove combinational loop on ack and stall Benjamin Herrenschmidt 2020-06-12 21:48:01 +10:00
6c3a8bf417 bram: Remove combinational loop on stall Benjamin Herrenschmidt 2020-06-12 21:47:06 +10:00
e5aa0e9dc9 uart: Remove combinational loops on ack and stall signal Benjamin Herrenschmidt 2020-06-12 21:46:37 +10:00
6aadad5a75 spi: Add booting from flash to litedram init Benjamin Herrenschmidt 2020-06-10 13:35:18 +10:00
a89e1469ef spi: Add simulation support Benjamin Herrenschmidt 2020-06-10 13:35:10 +10:00
801bd3b8ee flash-arty: update error message (#203) Dan Horák 2020-06-13 00:46:28 +02:00
9b458a9aa6 dmi: Add ASYNC_REG attribute on synchronizers (#200) Benjamin Herrenschmidt 2020-06-13 08:44:43 +10:00
d266c9e67d icache: Latch PLRU victim output (#199) Benjamin Herrenschmidt 2020-06-13 08:43:47 +10:00
41d28bbdfc Merge pull request #198 from ozbenh/litedram Paul Mackerras 2020-06-13 08:01:55 +10:00
cc4dcb3597 spi: Add SPI Flash controller Benjamin Herrenschmidt 2020-06-05 11:32:08 +10:00
15467fe536 litedram: L2 use latched refill_index Benjamin Herrenschmidt 2020-06-11 20:18:24 +10:00
05bbbf0772 litedram: Pipeline store acks in L2 Benjamin Herrenschmidt 2020-06-10 23:45:42 +10:00
5ae5f76558 arty/nexys-video: Update XDC Benjamin Herrenschmidt 2020-06-10 19:06:02 +10:00
b58ff724f6 litedram: Add stash buffer to the L2 cache wishbone interface Benjamin Herrenschmidt 2020-06-10 16:47:18 +10:00
b23fd6c5f1 litedram: Defer clearing of tags & valids to improve timing Benjamin Herrenschmidt 2020-06-10 18:00:12 +10:00
7192ee825f litedram: Improve dram_tb error output Benjamin Herrenschmidt 2020-06-10 17:58:27 +10:00
7577cb18fb Merge pull request #201 from mikey/github-actions Anton Blanchard 2020-06-12 10:25:09 +10:00
9653b2952f Move from travis to github workflow Michael Neuling 2020-06-10 09:57:15 +10:00
6bb3837b33 Merge pull request #194 from ozbenh/misc Paul Mackerras 2020-06-10 19:37:01 +10:00
183d05de86 gitignore: Add more exlusions Benjamin Herrenschmidt 2020-06-10 13:14:00 +10:00
63f10450a6 litedram: Fix DRAM init mem using too many address bits Benjamin Herrenschmidt 2020-06-10 08:36:44 +10:00
a93d9e77c9 litedram: Remove remnants of riscv-inits Benjamin Herrenschmidt 2020-06-05 22:28:30 +10:00
3c99e6c31f mw_debug: Add "save" function to save memory to a file Benjamin Herrenschmidt 2020-06-04 20:25:57 +10:00
3167515069 sw: Properly mask syscon register fields Benjamin Herrenschmidt 2020-06-04 11:56:47 +10:00
13da4caafb Merge pull request #196 from ozbenh/makefile-lib-fix Michael Neuling 2020-06-10 09:54:35 +10:00
0739b55bc2 Merge pull request #195 from shenki/nexys-video Michael Neuling 2020-06-10 09:22:50 +10:00
097d19fd32 Makefile: Improve unisim library generation Benjamin Herrenschmidt 2020-06-10 08:31:49 +10:00
fcdc01aa05 flash-arty: Re-add support for running from any path Joel Stanley 2020-06-09 11:22:57 +09:30
002858ddde flash-arty: Support Nexys Video's a200 Joel Stanley 2020-06-09 10:12:42 +09:30
e46c46ab5f Merge pull request #193 from paulusmack/master Michael Neuling 2020-06-05 20:17:01 +10:00
cff40237c7 Merge pull request #182 from mikey/travis Paul Mackerras 2020-06-05 18:02:33 +10:00
b863791e38 icache: Fix icbi potentially clobbering the icache (#192) Benjamin Herrenschmidt 2020-06-05 16:23:23 +10:00
afa82bea9c decode2: Reformat to 4-space indentation Paul Mackerras 2020-06-05 11:16:56 +10:00
d5c8c33bae decode1: Reformat to 4-space indentation Paul Mackerras 2020-06-05 11:16:07 +10:00
af909840e6 decode1: Make ld/std and lwa not be single-issue Paul Mackerras 2020-06-01 16:42:05 +10:00
a740c4b7af Improve Travis to run as a matrix job Michael Neuling 2020-05-23 17:00:24 +10:00
6323f27423 Add unit tests to check and check_light Michael Neuling 2020-05-24 12:09:11 +10:00
809933a567 Add unit tests make target Michael Neuling 2020-05-24 12:08:47 +10:00
560a6f6b18 Add tests_console make target Michael Neuling 2020-05-23 16:59:51 +10:00
983f4fefe1 Merge pull request #191 from ozbenh/litedram Paul Mackerras 2020-06-05 13:16:56 +10:00
b0e15f2fb5 litedram: Make the L2 twice as tall Benjamin Herrenschmidt 2020-06-05 11:45:00 +10:00
4a4a98d4b9 core: Do addpcis using the main adder (#189) Paul Mackerras 2020-06-05 11:29:31 +10:00
599fad117b litedram: Remove old "VexRiscV" based initializations Benjamin Herrenschmidt 2020-06-05 11:15:35 +10:00
f089f2145a Merge pull request #183 from shawnanastasio/addpcis Paul Mackerras 2020-06-05 10:54:00 +10:00
eaf6883e57 litedram: Update to latest LiteX/LiteDRAM version Benjamin Herrenschmidt 2020-06-01 23:58:47 +10:00
6828e93113 litedram: Test bench Benjamin Herrenschmidt 2020-06-02 08:32:17 +10:00
a3857aac94 litedram: Add an L2 cache with store queue Benjamin Herrenschmidt 2020-05-27 11:06:51 +10:00
bf1b98b958 litedram: Add support for booting without BRAM Benjamin Herrenschmidt 2020-05-25 20:20:59 +10:00
6fe077910b litedram: Add simulation support Benjamin Herrenschmidt 2020-05-22 18:43:50 +10:00
42e138e539 Merge pull request #185 from ozbenh/misc Paul Mackerras 2020-06-05 09:29:24 +10:00
831ffceec7 Merge pull request #188 from ozbenh/openocd-tweaks Michael Neuling 2020-06-05 08:38:18 +10:00
d3c274d01e flash-arty: Add support for specifying the file type Benjamin Herrenschmidt 2020-06-04 23:29:29 +10:00
3592be733e flash-arty: Support hex values for address Benjamin Herrenschmidt 2020-06-04 23:13:45 +10:00
62233eddd7 Merge pull request #168 from shenki/flash-arty Paul Mackerras 2020-06-03 14:20:02 +10:00
ecaa5e2fb2 dcache: Rework RAM wrapper to synthetize better on Xilinx Benjamin Herrenschmidt 2020-05-25 16:48:47 +10:00
a9178ed0c1 bin2hex: Make sure to generate little endian files Benjamin Herrenschmidt 2020-06-01 18:24:15 +10:00
b8df0647fd mw_debug: Fix memory overflow with "sim" backend Benjamin Herrenschmidt 2020-05-29 00:04:46 +10:00
84ab28b3d2 Merge pull request #178 from antonblanchard/intercon Anton Blanchard 2020-06-02 11:54:00 +10:00
4c1a73131b Merge pull request #184 from antonblanchard/verific Anton Blanchard 2020-06-02 10:36:06 +10:00
ad1c8e7e14 Delete bit rotted verific script Michael Neuling 2020-05-26 16:55:20 +10:00
8b161c6dc6 Add a new misc test suite with addpcis tests Shawn Anastasio 2020-05-25 20:08:59 -05:00
e606772aeb Implement the addpcis instruction Shawn Anastasio 2020-05-25 20:03:02 -05:00
12f36b4a35 litedram: Split the init memory from the main wrapper Benjamin Herrenschmidt 2020-05-20 21:00:27 +10:00
f86fb74bfe irq: Simplify xics->core irq input Benjamin Herrenschmidt 2020-05-17 15:04:23 +10:00
573b6b4bc4 soc: Rework interconnect Benjamin Herrenschmidt 2020-05-11 21:22:07 +10:00
8d64090a68 sw: Add full memory map to .h and use it for litedram .lds Benjamin Herrenschmidt 2020-05-15 17:43:51 +10:00
bdb428a40b Merge pull request #181 from antonblanchard/Makefile-rework-2 Anton Blanchard 2020-05-23 16:50:12 +10:00
04c56a0c52 Pass clock frequency to UART sim wrapper Anton Blanchard 2020-05-23 13:46:43 +10:00
cb25167220 Merge pull request #180 from antonblanchard/Makefile-rework Anton Blanchard 2020-05-21 12:29:55 +10:00
7b14819dbb A little less shouting in the Makefile Anton Blanchard 2020-05-20 16:27:06 +10:00
01da807476 Fix the simulated DMI Anton Blanchard 2020-05-20 16:18:58 +10:00
ab86b58d95 Exit cleanly from testbench on success Anton Blanchard 2020-05-20 16:07:13 +10:00
a9e7194de5 Merge Makefile and Makefile.synth Anton Blanchard 2020-05-20 15:37:49 +10:00
6326efaca4 Add Makefile command line variables to enable docker and podman Anton Blanchard 2020-05-20 15:01:42 +10:00
224e7734a8 Rework Makefile Anton Blanchard 2020-05-20 14:29:50 +10:00
b82d07c8d5 Merge pull request #179 from antonblanchard/yosys-verilator Anton Blanchard 2020-05-19 15:53:54 +10:00
8c028f26f1 Improve make clean Anton Blanchard 2020-05-19 15:32:04 +10:00
3e8a6a8fc2 Add yosys/verilator support Anton Blanchard 2020-05-19 15:18:42 +10:00
354e0fbfea Merge pull request #171 from shenki/mw-debug-features Anton Blanchard 2020-05-19 14:27:42 +10:00
6692f0db4f Merge pull request #173 from Jbalkind/core-vcs-syntax Anton Blanchard 2020-05-19 14:04:19 +10:00
5860c2d1b6 mw_debug: Add README Joel Stanley 2020-05-11 13:52:41 +09:30
2bf5bf4bac mw_debug: Add usage text Joel Stanley 2020-05-10 13:30:26 +09:30
fa90f0dbb1 mw_debug: Add CFLAGS and fix warnings Joel Stanley 2020-05-11 13:22:00 +09:30
6d36ef93d9 Merge pull request #177 from antonblanchard/litedram Anton Blanchard 2020-05-19 13:32:33 +10:00
4e78b8078e Merge branch 'master' into litedram Anton Blanchard 2020-05-19 12:28:02 +10:00
e9251544f4 Merge pull request #176 from antonblanchard/console-improv Anton Blanchard 2020-05-19 11:53:34 +10:00
03369a137c Merge pull request #175 from antonblanchard/yosys-fixes-2 Anton Blanchard 2020-05-19 11:38:16 +10:00

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