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399 Commits 11 Branches 9 Tags
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Author SHA1 Message Date
Katherine Watson
7a6d5d3fc9 Make serv_alu.v synthesizable with Vivado 2023-11-16 14:41:46 +01:00
Olof Kindgren
c7fc57213c Avoid releasing trap signal too early 
The trap signal is used my the mux in serv_rf_if to decide which
registers to write to. If the trap signal is dropped too early,
the destination address changes while the register is still being
written to.
 2023-10-31 22:21:12 +01:00
uhit332
46a820ee42 support for W=4 2023-10-31 15:53:36 +01:00
uhit332
f9d6b23543 support for W=4 2023-10-31 13:23:17 +01:00
Olof Kindgren
a8fbf688c5 Fix RTD CI action failures 2023-10-31 12:45:31 +01:00
uhit332
2e23b5313a alu with support for W=4 2023-10-31 12:42:52 +01:00
Olof Kindgren
ed4b8198ac Skip disassembly of test cases in riscof plugin 
Disassembly takes a lot of time with some toolchains, so leave that
to the user instead.
 2023-07-21 12:25:25 +02:00
Olof Kindgren
4567214721 Refactor counter in serv_state 2023-07-13 10:29:19 +02:00
Olof Kindgren
f0f2dba67f Add PC tracing capability 
This adds the --trace_pc option to dump the PC after each instruction to a file
called trace.bin
 2023-07-12 22:00:36 +02:00
Olof Kindgren
9bb2f95bf4 Tidy up GH Actions naming 2023-07-10 15:07:38 +02:00
Olof Kindgren
c6e5053c78 Clean up RISCOF support structure 
The RISCOF regression test suite can now be run from a workspace instead
of having to be run from inside the repo. Also removes the need for a
submodule.
 2023-07-10 15:06:13 +02:00
Olof Kindgren
cd3b587364 Add linting for servant and serving to Github actions 2023-06-22 15:49:04 +02:00
Olof Kindgren
8edd456b5d Rewrite serv_rf_ram_if 
This adds some optimizations to serv_rf_ram_if. It also adds a read enable
signal and delays writes one cycle which has the added bonus that no reads
or writes happen in the same cycle for RF_WIDTH > 2. This allows SERV to be
used with single-port RAMs in most cases.
 2023-06-22 15:48:25 +02:00
Olof Kindgren
a6e4d82a30 Enable support for tickless timer driver 2023-06-21 23:19:26 +02:00
Calder Coalson
1268538f9d Add Arty S7-50 support 2023-06-15 18:17:52 +00:00
Olof Kindgren
d4491f1060 Add initial Serving porting information 2023-06-13 09:30:36 +02:00
Olof Kindgren
6893791d01 Add resource table to README 2023-05-18 22:27:08 +02:00
Olof Kindgren
a03f283d74 Clean up servant core file 2023-05-17 12:20:56 +02:00
Olof Kindgren
1327774f02 Fix CMOD A7 servant target 2023-05-17 10:13:02 +02:00
Olof Kindgren
d7006634cb Remove old LibeCores badge 2023-05-14 22:17:37 +02:00
Olof Kindgren
6d980810f9 Update README 2023-05-11 23:27:25 +02:00
Olof Kindgren
f62062d481 Add readthedocs config file 2023-05-11 22:48:11 +02:00
Olof Kindgren
37724d8d9f Fix Github actions 
Repair the lint and CI actions. Add formal verification.
 2023-05-07 22:33:49 +02:00
Olof Kindgren
af230d517b Migrate lint, nexys_a7, tinyfpga_bx and verilator_tb targets to flow API 2023-04-30 21:49:42 +02:00
Olof Kindgren
109acd0a53 Prepare for release 1.2.1 2022-12-25 22:04:52 +01:00
Olof Kindgren
5fa5c5c3c3 Sort all sections in servant.core 2022-12-25 21:49:19 +01:00
Olof Kindgren
9be55f5cad Set align parameter to the value of compressed by default 2022-12-25 21:34:48 +01:00
Abdulwadoodd
04991380df GitHub actions for updated Compliance testing 2022-12-25 21:23:51 +01:00
Abdulwadoodd
174330d06e Updated readme and added instructions to run compliance tests 2022-12-25 21:23:51 +01:00
Abdulwadoodd
121099bf54 Add SAIL-RISCV binaries with reamde instructions 2022-12-25 21:23:51 +01:00
Abdulwadoodd
c1a275db49 Added arch-tests as a submodule 2022-12-25 21:23:51 +01:00
Abdulwadoodd
41ae06f6cf Update Compliance testing framework 2022-12-25 21:23:51 +01:00
Abdulwadoodd
1bdd42acb5 Deleted old compliance framework 2022-12-25 21:23:51 +01:00
Olof Kindgren
76a75995b9 Remove RVFI interface from synth wrapper 2022-12-25 20:05:52 +01:00
Olof Kindgren
9c1685e07e Add Servant documentation 2022-12-18 18:09:54 +01:00
Olof Kindgren
7c004e8f7b Add reset input for Arty A7 target 2022-10-16 20:04:56 +02:00
gojimmypi
6ad60f69a2 Add ICE-V Wireless support 2022-10-13 10:23:13 +02:00
Olof Kindgren
7abd9bbbe1 serving: Tie off extension interface 2022-10-13 09:58:21 +02:00
Eric Brombaugh
5cc7b0cbe1 Guarantee at least 2 cycles of o_rst after PLL locked. 2022-08-10 09:02:51 +00:00
Olof Kindgren
cb4276e8b2 Prepare for release 1.2.0 2022-07-26 01:19:28 +02:00
Olof Kindgren
efe8ba832a Set up Github CI testing matrix for compliance tests 2022-07-26 00:28:53 +02:00
Abd
0cce381316 Add Nexys 2 target info 2022-07-26 00:28:53 +02:00
Olof Kindgren
73508bc5de Expose with_csr in servant 2022-07-26 00:28:53 +02:00
Abdulwadoodd
be06cd21c2 Right version of riscv-arch-test 2022-07-26 00:28:53 +02:00
Abd
1beb9d33ec privilege tests fixed for rv32i 2022-07-26 00:28:53 +02:00
Inoki
302224834b Add description for AX309 board target 2022-06-13 12:21:05 +00:00
Inoki
e996b5498a Add Alinx AX309 board as a target 
Running at 32MHz with 115200 baud rate UART (using the on-board RS232)
 2022-06-13 12:21:05 +00:00
Olof Kindgren
2611c89cbe Update support for compliance tests version 2.7.4 2022-06-13 12:02:27 +00:00
Abd
a8f7de9e8c compressed parameter added for Nexys-2 FPGA target 2022-06-13 10:38:36 +00:00
Abd
82b410f500 Update reamde, comments and paramters 2022-06-13 10:38:11 +00:00