wfjm 14362b2a56 Add basic DDR memory support ...

- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model

2018-12-31 10:00:14 +01:00

..

bp_rs232_2l4l_iob.vbom

- interim release w11a_V0.531 (untagged)

2011-09-12 20:52:31 +00:00

bp_rs232_2l4l_iob.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

bp_rs232_2line_iob.vbom

- interim release w11a_V0.531 (untagged)

2011-09-12 20:52:31 +00:00

bp_rs232_2line_iob.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

bp_rs232_4line_iob.vbom

- interim release w11a_V0.531 (untagged)

2011-09-12 20:52:31 +00:00

bp_rs232_4line_iob.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

bp_swibtnled.vbom

- interim release w11a_V0.56 (untagged)

2013-01-02 21:06:53 +00:00

bp_swibtnled.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

bpgenlib.vbom

- interim release w11a_V0.562 (untagged)

2013-04-13 17:13:15 +00:00

bpgenlib.vhd

consolidate clock generation in 7-Series designs

2018-12-21 09:06:16 +01:00

bpgenrbuslib.vbom

- interim release w11a_V0.562 (untagged)

2013-04-13 17:13:15 +00:00

bpgenrbuslib.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

Makefile

comment&code cosmetics; minor changes

2018-11-11 09:50:46 +01:00

Makefile.ise

- Code base cleaned-up for vivado, fsm now inferred

2016-06-26 16:02:42 +00:00

rgbdrv_3x2mux.vbom

add Digilent Arty S7 board support

2018-08-25 07:58:05 +02:00

rgbdrv_3x2mux.vhd

add Digilent Arty S7 board support

2018-08-25 07:58:05 +02:00

rgbdrv_3x4mux.vbom

- Add Arty support (BRAM only)

2016-03-19 15:45:59 +00:00

rgbdrv_3x4mux.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

rgbdrv_analog_rbus.vbom

- Add Arty support (BRAM only)

2016-03-19 15:45:59 +00:00

rgbdrv_analog_rbus.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

rgbdrv_analog.vbom

- Add Arty support (BRAM only)

2016-03-19 15:45:59 +00:00

rgbdrv_analog.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

rgbdrv_master.vbom

- Add Arty support (BRAM only)

2016-03-19 15:45:59 +00:00

rgbdrv_master.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

s7_cmt_1ce1ce2c.vbom

Add basic DDR memory support

2018-12-31 10:00:14 +01:00

s7_cmt_1ce1ce2c.vhd

Add basic DDR memory support

2018-12-31 10:00:14 +01:00

s7_cmt_1ce1ce.vbom

consolidate clock generation in 7-Series designs

2018-12-21 09:06:16 +01:00

s7_cmt_1ce1ce.vhd

get ready for w11a_V0.753 release

2018-12-29 14:14:08 +01:00

sn_7segctl.vbom

- added support for Vivado

2015-03-09 19:26:25 +00:00

sn_7segctl.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

sn_humanio_demu_rbus.vbom

- interim release w11a_V0.561 (untagged)

2013-01-06 16:19:26 +00:00

sn_humanio_demu_rbus.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

sn_humanio_demu.vbom

- interim release w11a_V0.532 (untagged)

2011-11-20 12:31:43 +00:00

sn_humanio_demu.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

sn_humanio_emu_rbus.vbom

Add Digilent Cmod A7 (35 die size) support

2017-06-28 22:29:09 +02:00

sn_humanio_emu_rbus.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

sn_humanio_rbus.vbom

- interim release w11a_V0.531 (untagged)

2011-09-12 20:52:31 +00:00

sn_humanio_rbus.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00

sn_humanio.vbom

- added support for Vivado

2015-03-09 19:26:25 +00:00

sn_humanio.vhd

get disclaimers in line with GPL V3 License.txt

2018-01-02 21:57:40 +01:00