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Author SHA1 Message Date
Benjamin Herrenschmidt
42d802bed0 Add distclean to Makefile 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 16:46:31 +10:00
Benjamin Herrenschmidt
fe275effeb New C based JTAG debug tool 
This works with both the sim socket and urjtag, and supports the
new core functions, loading a file in memory etc...

The code still needs a lot of cleanup and a help!

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 16:46:31 +10:00
Benjamin Herrenschmidt
98f0994698 Add core debug module 
This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
 2019-09-20 16:45:50 +10:00
Benjamin Herrenschmidt
554b753172 Add jtag support in simulation via a socket 
This adds a local socket that can be used to communicate with
the debug tool (which will be committed separately) and generates
the JTAG signals.

We generate the low level JTAG signals, thus directly driving the
simulated BSCANE2, and the Xilinx DTM

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 15:07:49 +10:00
Benjamin Herrenschmidt
ad14a41d80 Add DMI address decoder 
And prepare signals for core DMI support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 15:07:49 +10:00
Benjamin Herrenschmidt
b46f81fae4 Wishbone debug module 
This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 15:07:49 +10:00
Benjamin Herrenschmidt
ee52fd4d80 Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs 
This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 15:07:49 +10:00
Benjamin Herrenschmidt
1206dfe18c Use a 3 way WB arbiter and cleanup fpga toplevel 
The 3rd master is currently unused, it will host the WB debug module.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-20 15:07:47 +10:00
Anton Blanchard
6571b13308 Merge pull request #66 from antonblanchard/reformat-4 
More reformatting
 2019-09-19 22:49:41 +10:00
Anton Blanchard
7e7010c304 Reformat crhelpers, and remove some stale code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:53:27 +10:00
Anton Blanchard
ae42370d24 Reformat helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:53:09 +10:00
Anton Blanchard
9ff86a62f5 Reformat insn_helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:52:07 +10:00
Anton Blanchard
c5d327cebf Merge pull request #65 from antonblanchard/loadstore-opt 
A small loadstore optimisation, and some reformatting
 2019-09-19 21:48:22 +10:00
Anton Blanchard
687051ecbb Reformat loadstore1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:37:43 +10:00
Anton Blanchard
6e442e07a5 Reformat loadstore2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:36:51 +10:00
Anton Blanchard
e1a71e4545 loads don't do both byte reversal and sign extension 
Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:31:34 +10:00
Anton Blanchard
4df05e0598 Merge pull request #64 from antonblanchard/reformat-3 
Reformat some more files
 2019-09-19 21:07:31 +10:00
Anton Blanchard
48f4dcece8 Merge pull request #63 from antonblanchard/multiply-cleanup 
Multiply cleanup
 2019-09-19 20:36:26 +10:00
Anton Blanchard
df1165bdfc Reformat wishbone code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:35:42 +10:00
Anton Blanchard
06392e7eaa Reformat glibc_random 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:33:58 +10:00
Anton Blanchard
1d5e8c2eb4 Reformat simple_ram_behavioural 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:32:07 +10:00
Anton Blanchard
fd9e971b2c Reformat sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:28:37 +10:00
Anton Blanchard
28e6d343dc Reformat multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:26:55 +10:00
Anton Blanchard
fc10935797 Reformat execute2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:24:29 +10:00
Anton Blanchard
4d0afa3a6d Reformat CR file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:22:36 +10:00
Anton Blanchard
4d9b2a1165 Reformat register file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:21:58 +10:00
Anton Blanchard
8dd97fbe7f Reformat multiply code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:19:46 +10:00
Anton Blanchard
99dd4de54e Don't use VHDL 2008 condition operator in multiply 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:18:01 +10:00
Anton Blanchard
550b2b8608 Merge pull request #62 from antonblanchard/byte-reverse-store-opt 
Move byte reversal of stores to first cycle
 2019-09-16 13:17:37 +10:00
Anton Blanchard
135805d2ac Merge pull request #61 from antonblanchard/execute-cleanup 
execute1 no longer needs sim_console
 2019-09-16 13:14:25 +10:00
Anton Blanchard
a061924a78 Move byte reversal of stores to first cycle 
We are seeing some timing issues with the second cycle of loadstore,
and  we aren't doing much in the first cycle, so move it here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:49:44 +10:00
Anton Blanchard
6d85920068 execute1 no longer needs sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:18:53 +10:00
Anton Blanchard
a4c8dd860a Merge pull request #60 from antonblanchard/testbenches 
Add a few more test benches
 2019-09-15 22:52:14 +10:00
Anton Blanchard
1b6eef2a5d Fix multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:44:01 +10:00
Anton Blanchard
1e3e16e500 Add an icache testbench 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:13:21 +10:00
Anton Blanchard
d573748da0 Merge pull request #56 from antonblanchard/writeback-fix3 
Remove cycle in writeback
 2019-09-15 22:08:57 +10:00
Anton Blanchard
152261fac8 Remove cycle in writeback 
The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:47:59 +10:00
Anton Blanchard
7bb88d5321 Merge pull request #59 from antonblanchard/trap-decode 
Fix make check
 2019-09-15 21:37:47 +10:00
Anton Blanchard
f5a5b91736 Merge pull request #58 from antonblanchard/decode2-assert 
Fix spurious outstanding assert
 2019-09-15 21:30:30 +10:00
Anton Blanchard
427effdaa9 Fix make check 
We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.

All these trap instructions need to be resolved at completion, not
in execute.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:21:36 +10:00
Anton Blanchard
d813ffb748 Fix spurious outstanding assert 
Check it in the sequential process, not the combinatorial one.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:59:24 +10:00
Anton Blanchard
30aa16d8f3 Merge pull request #57 from antonblanchard/add-nop 
Add a decode for the nop instruction
 2019-09-15 18:34:27 +10:00
Anton Blanchard
9867fb6149 Add a decode for the nop instruction 
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:18:24 +10:00
Anton Blanchard
85062793b1 Merge pull request #55 from antonblanchard/fetch-fix 
Add a default value for RESET_ADDRESS
 2019-09-15 11:18:42 +10:00
Anton Blanchard
d52046104f Add a default value for RESET_ADDRESS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 10:38:49 +10:00
Anton Blanchard
71e45a82ee Merge pull request #51 from antonblanchard/writeback-fix 
Some writeback updates
 2019-09-15 09:55:10 +10:00
Anton Blanchard
e69e79d8af Reformat writeback.vhdl 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:07:34 +10:00
Anton Blanchard
50a361a5dc Exit if we try to write more than one GPR or CR in a cycle 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:04:47 +10:00
Anton Blanchard
ab34c48392 Merge pull request #50 from antonblanchard/decode1-opt 
No need to gate nia or insn in decode1
 2019-09-12 21:15:24 +10:00
Anton Blanchard
acdb2ea157 No need to gate nia or insn in decode1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 17:06:09 +10:00