j-core.j-core-ice40

mirror of https://github.com/j-core/j-core-ice40.git synced 2026-03-05 18:59:03 +00:00

Author	SHA1	Message	Date
J	fb8fdd41c7	move back to ghdl because nvc can't trace records yet, even though it simulates them	2019-03-12 22:42:41 -04:00
J	93d011ba48	Add sim by default and wave viewer ctl file for reg file debug	2019-03-08 01:37:20 -05:00
J	d94eb15232	Actually add sim model for Lattice HF clk	2019-03-08 01:10:20 -05:00
J	dfd7c38c98	Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk	2019-03-08 01:09:52 -05:00
J	480c4cefe0	Pin mapping for EVB	2019-03-05 22:55:59 -05:00
J	f0dbd0a33e	correct outputs for Lattice EVB. Fix stack location. Still crashes with result code 0x11 on the LEDs	2019-03-05 02:17:06 -05:00
J	b1176ec9aa	First synthesys for ICE40 UP5k with everything to blink LEDs	2019-03-04 01:17:33 -05:00
J	4a6746a0b1	With single port RAM	2019-03-03 23:16:35 -05:00
J	a0acbcafdc	Add testrom, modified for small memory... enable tests if you need in Makefile	2019-03-03 20:55:24 -05:00
J	9e5f83edd9	Add in the test rom	2019-03-03 19:35:20 -05:00
J	ea1dd551f9	Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used	2019-03-03 17:29:03 -05:00
J	f35876f9bf	Regfile now uses sync ram, -ve clock read. Generics have defaults	2019-03-03 16:28:34 -05:00
J	eaad427655	Import from the git version found in work/nickg on my trash can mac	2019-03-03 14:48:57 -05:00