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Author	SHA1	Message	Date
Andrew Kay	d50f4f5030	wip	2020-03-18 21:26:36 -05:00
Andrew Kay	5f2dfeb5ec	Merge branch 'master' into i2	2020-03-14 10:46:20 -05:00
Andrew Kay	f4be7f39a2	Add data word packing functions	2020-03-14 10:43:55 -05:00
Andrew Kay	0785407a49	Add TX to top	2020-03-13 21:26:13 -05:00
Andrew Kay	debe68c4c3	Drop address from command packing functions	2020-03-13 08:13:42 -05:00
Andrew Kay	711d3ed1c8	Make word packing functions public	2020-03-13 08:08:01 -05:00
Andrew Kay	b750c9e756	Drop shims, for now	2020-03-03 19:52:56 -06:00
Andrew Kay	61e56a2dc3	PCB fabrication	2020-02-29 10:16:18 -06:00
Andrew Kay	aeb39bfb69	Added part numbers	2020-02-28 10:46:48 -06:00
Andrew Kay	0a92b621e8	Prototype PCB	2020-02-27 22:51:38 -06:00
Andrew Kay	891390cb84	Attempt DP8340 and DP8341 shims	2020-02-21 20:43:52 -06:00
Andrew Kay	49abcf7e2b	Add data, data_available and data_read	2020-02-18 07:55:13 -06:00
Andrew Kay	811a048685	Initial attempt at receiver	2020-02-17 20:47:46 -06:00
Andrew Kay	2b81a4a961	Clean up bit timer	2020-02-15 09:41:37 -06:00
Andrew Kay	81c6172e7b	Bit timer module	2020-02-14 20:13:01 -06:00
Andrew Kay	a95e83bd5e	Clean up full and data loading	2020-02-14 07:58:14 -06:00
Andrew Kay	a8f0949842	Parameterize tx_delay_buffer size	2020-02-14 06:57:50 -06:00
Andrew Kay	a7ee9c502d	Add tx_delay size comment	2020-02-13 19:26:17 -06:00
Andrew Kay	d4eaeecec2	Hello world	2020-02-12 23:13:21 -06:00
Andrew Kay	c859688931	Initial attempts at multiple word transmission	2020-02-12 19:44:43 -06:00
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	13eb0f52bd	Adding tx_inverted and updating pins	2020-02-10 22:26:39 -06:00
Andrew Kay	ff200bf26f	Adding tx_delay	2020-02-10 22:13:55 -06:00
Andrew Kay	7bf43eede5	Remove BIT_ALIGN state and improve active	2020-02-10 21:56:35 -06:00
Andrew Kay	05663ab5b7	End sequence	2020-02-09 14:53:23 -06:00
Andrew Kay	7a78447c6c	Cleanup clocks	2020-02-09 09:50:40 -06:00
Andrew Kay	42a46806c8	Parity bit	2020-02-09 09:35:00 -06:00
Andrew Kay	77821b3f11	Data	2020-02-08 20:03:13 -06:00
Andrew Kay	b9ed29bd4b	Code violation and sync bit	2020-02-08 19:03:36 -06:00
Andrew Kay	9faae78fd8	Quiesce pattern	2020-02-08 18:55:11 -06:00
Andrew Kay	0b618d6b35	Adding a 19 MHz clock	2020-02-08 17:43:09 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00
Andrew Kay	e24ba22a1f	pycoax 0.2.0 pycoax-0.2.0	2019-12-24 19:49:33 -06:00
Andrew Kay	3512a03911	Add build pycoax action	2019-12-24 19:03:58 -06:00
Andrew Kay	1eef4e40cb	Implement CLEAR	2019-12-23 20:07:54 -06:00
Andrew Kay	70f44bef89	Implement INSERT_BYTE	2019-12-23 19:55:32 -06:00
Andrew Kay	83d172572f	Implement LOAD_MASK, SEARCH_FORWARD and SEARCH_BACKWARD	2019-12-23 19:29:13 -06:00
Andrew Kay	1d2b522e65	Implement RESET	2019-12-23 18:15:32 -06:00
Andrew Kay	ff2a2de575	Implement READ_MULTIPLE	2019-12-22 15:14:24 -06:00
Andrew Kay	99e660ce71	Implement LOAD_SECONDARY_CONTROL	2019-12-22 15:13:09 -06:00
Andrew Kay	8243620083	Implement READ_DATA	2019-12-22 14:31:39 -06:00
Andrew Kay	43786c3e27	Implement LOAD_CONTROL_REGISTER	2019-12-22 14:23:32 -06:00
Andrew Kay	ae293168ac	Add POLL action	2019-12-21 12:44:04 -06:00
Andrew Kay	543af3cbef	Refactor execute to take command word	2019-12-21 09:57:29 -06:00
Andrew Kay	54efc3845b	Implemented READ_STATUS	2019-12-19 08:05:16 -06:00
Andrew Kay	a13bb7f865	Do not check parity when unpacking data words	2019-12-17 22:54:45 -06:00
Andrew Kay	0304a6a932	Fix terminal model mapping	2019-12-17 22:34:09 -06:00
Andrew Kay	5be647b0f6	Update interface1 schematic and PCB	2019-10-09 20:11:05 -05:00
Andrew Kay	d5f38a13a8	Adding character map example	2019-09-05 21:59:39 -05:00
Andrew Kay	30c8d5d24c	pycoax 0.1.2 pycoax-0.1.2	2019-07-06 09:06:58 -05:00