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Code Issues Releases Wiki Activity
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Commit Graph

61 Commits

Author SHA1 Message Date
Gyorgy Szombathelyi
ba53ccbeda Archie: TAB-SPACE cleanup in MiST toplevel 2019-12-13 19:33:26 +01:00
Gyorgy Szombathelyi
42a828913f Archie: register some SDRAM signals for better timing properties 2019-11-02 18:59:56 +01:00
Gyorgy Szombathelyi
b5883c7c2c [Archie] Risc Developments IDE interface 2019-11-02 18:59:34 +01:00
Gyorgy Szombathelyi
07de4fb657 Archie: eliminiate a < comparision in the SDRAM controller 2019-10-26 18:58:25 +02:00
Gyorgy Szombathelyi
ac7d7f55e7 Archie: optional scandoubler for 15kHz modes 2019-10-26 18:58:11 +02:00
Gyorgy Szombathelyi
1dbc66ab68 Archie: use a bit less cycles in the SDRAM controller 2019-10-23 14:56:12 +02:00
Gyorgy Szombathelyi
ada9089f7c Archie: force blanking of the back porch area 
Helps on BIA Bounce demo, Spectrum emulator
 2019-10-23 12:55:01 +02:00
Gyorgy Szombathelyi
f296e03f53 Archie: clean up SDRAM controller 2019-10-23 12:45:40 +02:00
Gyorgy Szombathelyi
db288bcdae Archie: don't consume new pixel data during hsync 
Fixes BIA bounce demo
 2019-10-22 19:57:08 +02:00
Gyorgy Szombathelyi
cb13fcef8d Archie: use 2 deterministic places for requesting new data in VIDC 2019-10-22 19:57:08 +02:00
Gyorgy Szombathelyi
ef4be11a52 Archie: vidc flybk should be active after the end of the display 
...until the first displayed one, according to the datasheet.

Fixes Elite in 15kHz
 2019-10-22 19:57:08 +02:00
Gyorgy Szombathelyi
434ea845de Archie: transfer hsync to cpuclk domain for using in MEMC 2019-10-21 19:52:32 +02:00
Gyorgy Szombathelyi
40e8f7e844 Archie: re-use the already fetched burst 
As a primitive 128 bit cache
 2019-10-21 17:37:06 +02:00
Gyorgy Szombathelyi
1b4884aaa6 Archie: fix possible bug when wb_we change too soon after wb_ack 2019-10-21 12:09:42 +02:00
Gyorgy Szombathelyi
4716d75bf5 Archie: update SDRAM testbench 2019-10-21 12:08:30 +02:00
Gyorgy Szombathelyi
1a4cdecac7 Archie: 128 bit burst read for VIDC 2019-10-20 20:30:34 +02:00
Gyorgy Szombathelyi
54d155bcf0 Archie: use built-in SDRAM burst feature 2019-10-20 13:35:53 +02:00
Gyorgy Szombathelyi
966e01d66c Revert "Archie: 128bit SDRAM interface (by Sorgelig)" 
This reverts commit 375c423a85.
 2019-10-19 23:30:50 +02:00
Gyorgy Szombathelyi
39fafc65b8 Archie: replace vidc fifo with DCFIFO component to fix clock domain crossing issues 2019-10-19 17:17:17 +02:00
Gyorgy Szombathelyi
4a1a470d0e Archie: change video timing events to simple equality checks 
Display event registers less likely to glitch
 2019-10-18 21:57:11 +02:00
Gyorgy Szombathelyi
375c423a85 Archie: 128bit SDRAM interface (by Sorgelig) 2019-10-18 20:56:39 +02:00
Gyorgy Szombathelyi
7122e993fc Archie: reduce clock to 40MHz 2019-10-18 20:39:40 +02:00
Gyorgy Szombathelyi
46bd0dd0c1 Archie: common FDC with the ST core 2019-10-18 19:54:03 +02:00
Gyorgy Szombathelyi
9b19a1f1b8 [Archie] Smart precharge for SDRAM 2019-03-08 01:11:47 +01:00
Gyorgy Szombathelyi
5135fd9854 [Archie] Spare some SDRAM cycles 2019-03-07 22:37:52 +01:00
Gyorgy Szombathelyi
d774f5356b [Archie] Adjust SDRAM simulation 2019-03-07 15:33:15 +01:00
Gyorgy Szombathelyi
dd445a01ca [Archie] Increase the CPU clock to 42MHz 2019-03-05 23:04:43 +01:00
Gyorgy Szombathelyi
84b9421d96 [Archie] Use the common clock for the PLL reconfiguration 2019-03-05 16:16:04 +01:00
Gyorgy Szombathelyi
bb0141b3a8 [Archie] Silence warnings 2019-03-05 15:57:36 +01:00
Gyorgy Szombathelyi
0ee6b5b8df [Archie] VIDC: there's no horizontal cursor end register 2019-03-05 13:40:48 +01:00
Gyorgy Szombathelyi
5d0683ab10 [Archie] Fix in user_io 2019-03-05 13:40:03 +01:00
Gyorgy Szombathelyi
ca812da031 [Archie] Remove obsolete files 2019-03-03 15:24:20 +01:00
Gyorgy Szombathelyi
b6c3910709 [Archie] FDC fixes 2019-03-03 14:51:45 +01:00
Gyorgy Szombathelyi
1d60379857 [Archie] Add CMOS RAM upload 2019-03-02 22:47:58 +01:00
Gyorgy Szombathelyi
860a597248 [Archie] Use standard IO for FDC with full read/write support 
Needs firmware update
 2019-03-02 16:43:56 +01:00
Gyorgy Szombathelyi
99d8c93590 [Archie] Synchronize reset signals in VIDC 2019-02-24 03:13:15 +01:00
Gyorgy Szombathelyi
41481485d1 [Archie] Fix and swap joysticks 2019-02-24 01:47:27 +01:00
Gyorgy Szombathelyi
d95c05a143 [Archie] Update user_io and data_io 2019-02-24 00:22:07 +01:00
Gyorgy Szombathelyi
c8d2bb5c00 [Archie] Use only one clock in the FDC 2019-02-24 00:21:28 +01:00
Gyorgy Szombathelyi
2ee8063202 [Archie] Restore VIDC enhancer 
- 24, 25, 36 MHz pixel clock via reconfigurable PLL
- 24 MHz mode gets composite sync
 2019-02-23 23:42:06 +01:00
Gyorgy Szombathelyi
51c6754a2f [Archie] Add composite sync switch via the scandoubler switch 2019-02-21 23:52:11 +01:00
Gyorgy Szombathelyi
5510e93b27 [Archie] Hold the CPU until the ROM is downloaded 2019-02-18 22:12:10 +01:00
Gyorgy Szombathelyi
da57e7d393 [Archie] Improve SDRAM controller 
Don't feed the SDRAM pins from combinatorial logic, that prevents
to use fast output registers.
 2019-02-14 20:55:53 +01:00
Gyorgy Szombathelyi
238678366b [Archie] Cleanup some unused files 2019-02-09 01:55:16 +01:00
Gyorgy Szombathelyi
e12192463a [Archie] Add YPbPr 2019-02-09 01:52:55 +01:00
Gyorgy Szombathelyi
dd9e400334 [Archie] Adjust SDRAM timings 2019-02-09 01:21:38 +01:00
Gyorgy Szombathelyi
8d83a61d1d [Archie] Use only clk_32 in user_io and ioc 2019-02-09 00:18:36 +01:00
Gyorgy Szombathelyi
7472f9339d [Archie] Use only one clock in vidc (port from MiSTer) 2019-02-08 12:32:34 +01:00
sleary78
76709ccebe accidentally wiped the qpf file 2016-05-24 10:46:40 +01:00
sleary78
08858e963d updates for boilerplates 2016-05-23 20:39:26 +01:00