rdolbeau.SBusFPGA

engine_code

option to disable upper lane in AES/GCM isntructions; disable them in the code

2021-09-05 09:56:14 -04:00

jareth_code

fix fill when leftovers are 16 aligned bytes

2022-04-01 19:11:16 +02:00

VintageBusFPGA_Common @ 2a3d6a9db0

update common

2022-10-31 17:04:42 +01:00

.gitignore

ignore OLD stuff

2022-01-29 11:24:45 +01:00

blit_cg6.c

rename blit to blit_cg6

2022-07-23 12:51:43 +02:00

blit_cg6.lds

rename blit to blit_cg6

2022-07-23 12:51:43 +02:00

blit_cg6.sh

rename blit to blit_cg6

2022-07-23 12:51:43 +02:00

blit_font.h

Font for the on-screen debug display

2021-10-30 10:04:12 +02:00

bw2_fb.py

Emulate a bw2 FB, mostly to test feasibility of 1bpp FB in Litex

2021-12-18 11:30:45 +01:00

bw2_init.fth

Emulate a bw2 FB, mostly to test feasibility of 1bpp FB in Litex

2021-12-18 11:30:45 +01:00

bw2.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

cg3_fb.py

Emulate a bw2 FB, mostly to test feasibility of 1bpp FB in Litex

2021-12-18 11:30:45 +01:00

cg3_init.fth

CG3 is usable as console and with X11, despite the ugly colors

2021-10-08 20:37:32 +02:00

cg3.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

cg6_accel.py

missing commits

2022-06-26 09:44:08 +02:00

cg6_fb.py

changes to be able to test cg3/cg6 support with original PROM contents

2022-01-08 10:34:34 +01:00

cg6_init.fth

proto CG6

2021-10-15 22:38:27 +02:00

cg6.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

engine.py

apply patch from betrusted-io/gateware commit 817e284a3d92037b8cb0686735578d2bb60853e9

2021-09-07 05:11:28 -04:00

fb_init.fth

oups, missing file

2022-01-29 11:15:10 +01:00

fbc_init.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

forth_to_migen_rom.sh

drop V1.0

2021-11-13 12:41:05 +01:00

goblin_jareth_define.fth

missing files?

2022-10-09 12:44:34 +02:00

goblin_jareth_init.fth

missing files?

2022-10-09 12:44:34 +02:00

goblin.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

jareth.py

missing commits

2022-06-26 09:44:08 +02:00

neorv32_trng_patched.vhd

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

prom_migen.bth

prom

2021-07-14 05:14:19 -04:00

prom_migen.fth

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

prom_V1_0.bth

version-specific proms

2021-09-20 12:45:07 -04:00

prom_V1_2.bth

version-specific proms

2021-09-20 12:45:07 -04:00

sbus_to_fpga_export.py

Replace engine-based Jareth by VexRiscv-based 'Jareth' based on NuBusFPGA's goblin accel; also shorten some Forth name to avoid namespace issues.

2022-08-15 10:28:39 +02:00

sbus_to_fpga_fsm.py

comments for burst_size

2022-09-03 11:27:47 +02:00

sbus_to_fpga_fsmstat.py

fix broken timeout, some (disabled, for testing) stat stuff

2021-10-30 10:02:33 +02:00

sbus_to_fpga_prom.py

move to shared goblin

2022-10-31 15:49:20 +01:00

sbus_to_fpga_soc.py

move blit_goblin to common

2022-10-31 16:38:07 +01:00

sbus_to_fpga_trng.py

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

sbusfpga_stat_ctl.c

ioctl on/off switch on stats + ctrl pgm

2021-08-23 04:48:05 -04:00

sdcard_access.fth

various updates, and prom driver for sdcard

2021-11-17 19:19:32 +01:00

sdcard.fth

better sd(ram|card) drivers

2021-11-19 21:27:38 +01:00

sdram_csr.fth

init sdram in PROM

2021-10-07 19:43:07 +02:00

sdram_init.fth

fix sdram prom config for 90 MHz sysclk

2022-01-25 23:13:57 +01:00

sdram_init.py

wb_master moved to common

2022-10-31 16:51:56 +01:00

VexRiscv_FbAccel.v

missing commits

2022-06-26 09:44:08 +02:00

ztex213_sbus.py

fix i2c support

2022-02-25 22:28:48 +01:00