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Commit Graph

21 Commits

Author SHA1 Message Date
wfjm
14362b2a56 Add basic DDR memory support
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
2018-12-31 10:00:14 +01:00
wfjm
cf6c0ed8e0 cleanup not longer used directory 2018-12-30 10:59:24 +01:00
wfjm
e1abc27983 comment&code cosmetics; minor changes 2018-11-11 09:50:46 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
2018-11-09 17:48:56 +01:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support
- new test bench driver tbrun, give automatized test bench execution
2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e1479d4e5d - Add Arty support (BRAM only)
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
2016-03-19 15:45:59 +00:00
Walter F.J. Mueller
4a032e9436 - added RH70/RP/RM big disk support
- many cleanups
2015-05-14 17:00:36 +00:00
Walter F.J. Mueller
e91847f8db - added support for Vivado
- added support for Nexys4 and Basys3 boards
- added RL11 disk support
- lots of documentation updated
2015-03-09 19:26:25 +00:00
Walter F.J. Mueller
d87ac86f53 - migrate to rlink protocol version 4
- Goals for rlink v4
    - 16 bit addresses (instead of 8 bit)
    - more robust encoding, support for error recovery at transport level
    - add features to reduce round trips
      - improved attention handling
      - new 'list abort' command
  - For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
2014-12-20 16:39:52 +00:00
Walter F.J. Mueller
093d540121 - The div instruction gave wrong results in some corner cases when either
divisor or quotient were the largest negative integer (100000 or -32768).
  This is corrected now, for details see ECO-026-div.txt
- some minor updates and fixes to support scripts
- xtwi usage and XTWI_PATH setup explained in INSTALL.txt
2014-08-10 14:32:48 +00:00
Walter F.J. Mueller
4732555297 - interim release w11a_V0.581 (untagged)
- new reference system
  - switched from ISE 13.3 to 14.7.
  - map/par behaviour changed, unfortunately unfavorably for w11a. 
    On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can 
    be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
2014-05-29 21:30:01 +00:00
Walter F.J. Mueller
99de9893cb - interim release w11a_V0.562 (untagged)
- C++ and Tcl based backend server: many support classes for interfacing to 
  w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler. 
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
2013-04-13 17:13:15 +00:00
Walter F.J. Mueller
f6775f7d05 - interim release w11a_V0.55 (untagged)
- added xon/xoff (software flow control) support to serport library
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
2011-12-23 10:38:59 +00:00
Walter F.J. Mueller
f2d0f39621 - interim release w11a_V0.54 (untagged)
- add Nexys3 port of w11a
2011-12-04 21:25:09 +00:00
Walter F.J. Mueller
3f455d5236 - interim release w11a_V0.532 (untagged)
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
e15295649e - interim release w11a_V0.531 (untagged)
- many small changes to prepare upcoming support for Spartan-6 and
  usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
2011-09-12 20:52:31 +00:00
Walter F.J. Mueller
16ce5b2091 - interim release w11a_V0.51 (untagged)
- migrate to ibus protocol verion 2
  - nexys2 systems now with DCM derived system clock supported
  - sys_w11a_n2 now runs with 58 MHz clksys
2010-11-27 23:17:50 +00:00
Walter F.J. Mueller
3335c61549 initial source upload (no docs yet) 2010-07-09 18:14:38 +00:00