- *.Doxyfile: update to 1.8.15 template format (from 1.8.7)
- tst_sram: define and use init_rbf_*
- rbd_rbmon: more robust ack,err trace when busy
- pdp11.vhd: define c_init_rbf_greset
- pdp11_core_rbus: rename state field rbinit to greset
- pdp11_sys70: add and use RESET_SYS; fix pdp11_mem70 reset
- test_cp_ibrbasics.tcl: use imap addresses for test area
- rbmoni/test_regs.tcl: add a few cntl logic tests
- rbmoni/util.tcl: streamline raw_check
- rw11/defs.tcl: define INIT bits
- rw11/tbench.tcl: bench_list: ignore whitespace and empty lines
- tst_sram/util.tcl: define INIT
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
rbus->ibus window. Replaces with a 4k word window for whole IO page.
- utilize rlink protocol version 4 features in w11a backend
- use attn notifies to dispatch attn handlers
- use larger blocks (7*512 rather 1*512 bytes) for rdma transfers
- use labo and merge csr updates with last block transfer
- this combined reduces the number of round trips by a factor 2 to 3,
and in some cases the throughput accordingly.
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
divisor or quotient were the largest negative integer (100000 or -32768).
This is corrected now, for details see ECO-026-div.txt
- some minor updates and fixes to support scripts
- xtwi usage and XTWI_PATH setup explained in INSTALL.txt
- C++ and Tcl based backend server: many support classes for interfacing to
w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler.
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
