- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
rbus->ibus window. Replaces with a 4k word window for whole IO page.
- utilize rlink protocol version 4 features in w11a backend
- use attn notifies to dispatch attn handlers
- use larger blocks (7*512 rather 1*512 bytes) for rdma transfers
- use labo and merge csr updates with last block transfer
- this combined reduces the number of round trips by a factor 2 to 3,
and in some cases the throughput accordingly.
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
divisor or quotient were the largest negative integer (100000 or -32768).
This is corrected now, for details see ECO-026-div.txt
- some minor updates and fixes to support scripts
- xtwi usage and XTWI_PATH setup explained in INSTALL.txt
- new reference system
- switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
- C++ and Tcl based backend server now fully functional, supports with
DL11, RK11, LP11 and PC11 all devices available in w11a designs
- the old perl based backend server (pi_rri) is obsolete and removed
- operating system kits reorganized
- new C++ and Tcl based backend server supports now RK11 handling
- w11a systems operate with rlink over USB on nexsy2 and nexsy3 boards.
See w11a_os_guide.txt for details
- C++ and Tcl based backend server: many support classes for interfacing to
w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler.
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
