Anton Blanchard
8293ade696
Need reg on pll_bypass.v outputs
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-03 10:37:00 +11:00
Anton Blanchard
c4ac79c1d7
Merge pull request #7 from antonblanchard/makefile-cleanup
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Makefile: Add PLL variable
2020-02-02 21:46:45 +11:00
Anton Blanchard
7fe392d06b
Makefile: Add PLL variable
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:25:43 +11:00
Anton Blanchard
5abdf7ce5c
Merge pull request #6 from antonblanchard/fusesoc
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FuseSoC Support
2020-02-02 14:24:30 +11:00
Anton Blanchard
ae8466e8de
Reformat toplevel.v
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
c942fba2a9
Reformat PLLs
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
d2e04d01ff
Add pll_bypass.v
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
43e1e73ce8
Rename PLL
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Now we have multiple PLLs it makes no sense to call it pll_ecp5_evn.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
d0a15b35de
Move PLLs into pll/
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Also rename pll_ecp5_evn.v to pll_ehxplll.v
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
e3990af2ef
Add FuseSoC support
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 14:03:00 +11:00
Anton Blanchard
df3a74798e
Add a parameter to control the polarity of reset
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-02-02 09:02:33 +11:00
Anton Blanchard
fb166bbfae
Merge pull request #4 from antonblanchard/orange-crab-reset
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Invert OrangeCrab reset
2020-01-31 08:26:27 +11:00
Anton Blanchard
843749403f
Invert OrangeCrab reset
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-31 08:15:34 +11:00
Anton Blanchard
b44faeb038
Merge pull request #3 from antonblanchard/micropython-test
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Add a micropython test
2020-01-31 06:43:58 +11:00
Anton Blanchard
8f8382a2a9
Add a micropython test
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-31 06:33:40 +11:00
Anton Blanchard
df8ee8b4fb
Merge pull request #2 from antonblanchard/travis
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Initial Travis CI file
2020-01-31 05:34:11 +11:00
Anton Blanchard
ebce5ccedb
Initial Travis CI file
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-31 05:19:39 +11:00
Anton Blanchard
593c183c8c
Fix some compiler warnings in uart.c
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-31 05:14:44 +11:00
Anton Blanchard
63ed617cb6
Remove SystemVerilog syntax
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Lattice Diamond doesn't seem to support SystemVerilog which is a bit
depressing. We only use the syntax in a few places, so fix that up.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-31 02:49:26 +11:00
Anton Blanchard
1aeb5dad28
Remove an unused bit from the Divider
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 18:23:01 +11:00
Anton Blanchard
08ca3da14e
Remove some old tests
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These modules aren't used any more.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 18:11:46 +11:00
Anton Blanchard
858ac3281c
Fix a few issues in toplevel.v
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Vivado and verilator flagged a few issues.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 18:11:46 +11:00
Anton Blanchard
dc1c8e6278
Merge pull request #1 from gromero/master
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Add some notes on ECP5 setup
2020-01-30 08:40:35 +11:00
Gustavo Romero
d9dad9e8e9
Add some notes on ECP5 setup
2020-01-29 18:32:35 -03:00
Anton Blanchard
755c90b4fa
Fix typo in toplevel signal name
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I must have screwed this up when adding the PLL. It's surprising
that yosys didn't complain.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 07:56:24 +11:00
Anton Blanchard
729c02c8c9
Fix another reference to Makefile.synth in README.md
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 07:35:23 +11:00
Anton Blanchard
9b13565996
Update README.md
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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2020-01-30 07:27:04 +11:00
Anton Blanchard
f138ab7c7c
Initial import
2020-01-30 05:20:07 +11:00
