github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-01-29 04:51:16 +00:00
Code Releases Activity
143 Commits 39 Branches 0 Tags
8dd97fbe7ff41d5d40275de09b67883efc2b9c47
Commit Graph

143 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Anton Blanchard
8dd97fbe7f Reformat multiply code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:19:46 +10:00
Anton Blanchard
99dd4de54e Don't use VHDL 2008 condition operator in multiply 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:18:01 +10:00
Anton Blanchard
550b2b8608 Merge pull request #62 from antonblanchard/byte-reverse-store-opt 
Move byte reversal of stores to first cycle
 2019-09-16 13:17:37 +10:00
Anton Blanchard
135805d2ac Merge pull request #61 from antonblanchard/execute-cleanup 
execute1 no longer needs sim_console
 2019-09-16 13:14:25 +10:00
Anton Blanchard
a061924a78 Move byte reversal of stores to first cycle 
We are seeing some timing issues with the second cycle of loadstore,
and  we aren't doing much in the first cycle, so move it here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:49:44 +10:00
Anton Blanchard
6d85920068 execute1 no longer needs sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:18:53 +10:00
Anton Blanchard
a4c8dd860a Merge pull request #60 from antonblanchard/testbenches 
Add a few more test benches
 2019-09-15 22:52:14 +10:00
Anton Blanchard
1b6eef2a5d Fix multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:44:01 +10:00
Anton Blanchard
1e3e16e500 Add an icache testbench 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:13:21 +10:00
Anton Blanchard
d573748da0 Merge pull request #56 from antonblanchard/writeback-fix3 
Remove cycle in writeback
 2019-09-15 22:08:57 +10:00
Anton Blanchard
152261fac8 Remove cycle in writeback 
The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:47:59 +10:00
Anton Blanchard
7bb88d5321 Merge pull request #59 from antonblanchard/trap-decode 
Fix make check
 2019-09-15 21:37:47 +10:00
Anton Blanchard
f5a5b91736 Merge pull request #58 from antonblanchard/decode2-assert 
Fix spurious outstanding assert
 2019-09-15 21:30:30 +10:00
Anton Blanchard
427effdaa9 Fix make check 
We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.

All these trap instructions need to be resolved at completion, not
in execute.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:21:36 +10:00
Anton Blanchard
d813ffb748 Fix spurious outstanding assert 
Check it in the sequential process, not the combinatorial one.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:59:24 +10:00
Anton Blanchard
30aa16d8f3 Merge pull request #57 from antonblanchard/add-nop 
Add a decode for the nop instruction
 2019-09-15 18:34:27 +10:00
Anton Blanchard
9867fb6149 Add a decode for the nop instruction 
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:18:24 +10:00
Anton Blanchard
85062793b1 Merge pull request #55 from antonblanchard/fetch-fix 
Add a default value for RESET_ADDRESS
 2019-09-15 11:18:42 +10:00
Anton Blanchard
d52046104f Add a default value for RESET_ADDRESS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 10:38:49 +10:00
Anton Blanchard
71e45a82ee Merge pull request #51 from antonblanchard/writeback-fix 
Some writeback updates
 2019-09-15 09:55:10 +10:00
Anton Blanchard
e69e79d8af Reformat writeback.vhdl 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:07:34 +10:00
Anton Blanchard
50a361a5dc Exit if we try to write more than one GPR or CR in a cycle 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:04:47 +10:00
Anton Blanchard
ab34c48392 Merge pull request #50 from antonblanchard/decode1-opt 
No need to gate nia or insn in decode1
 2019-09-12 21:15:24 +10:00
Anton Blanchard
acdb2ea157 No need to gate nia or insn in decode1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 17:06:09 +10:00
Anton Blanchard
0e6861e5db Merge pull request #49 from antonblanchard/icache-2 
Add a simple direct mapped icache
 2019-09-12 16:14:28 +10:00
Anton Blanchard
89849a6856 Add a simple direct mapped icache 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 15:57:00 +10:00
Anton Blanchard
6cbf456388 SOC memory wishbone should clear ACK regardless of STB 
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 15:57:00 +10:00
Anton Blanchard
67446709ca Merge pull request #48 from antonblanchard/clk_gen_bypass 
Fix clk_gen_bypass
 2019-09-12 13:03:33 +10:00
Anton Blanchard
d89a9929fd Fix clk_gen_bypass 
I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 12:25:18 +10:00
Anton Blanchard
80aa781454 Merge pull request #47 from antonblanchard/if-fix 
Explicitly check against '1' in if statements
 2019-09-12 09:46:22 +10:00
Anton Blanchard
ca6f84efd6 Merge pull request #46 from antonblanchard/record-fix 
Remove names from end record statements
 2019-09-12 09:46:01 +10:00
Anton Blanchard
b9e28598b4 Explicitly check against '1' in if statements 
nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 09:19:31 +10:00
Anton Blanchard
142a722ce4 Remove names from end record statements 
These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 09:04:02 +10:00
Anton Blanchard
43f81773b4 Merge pull request #45 from antonblanchard/fixes 
Fix a couple of issues in the recent pipelining merge
 2019-09-11 22:53:47 +10:00
Anton Blanchard
7caf71ba71 Fix issue in loadstore1 
We weren't using the register in this stage.

Fixes: 819f820090 ("Register outputs on loadstore1")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 22:40:53 +10:00
Anton Blanchard
95442cd62c Fix issue in execute2 
We weren't using the register in this stage.

Fixes: c7aa683ba8 ("Register outputs on execute2")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 22:39:30 +10:00
Anton Blanchard
1ba84b56dd Merge pull request #44 from antonblanchard/nia-remove 
Remove nia from loadstore and multiply
 2019-09-11 21:58:01 +10:00
Anton Blanchard
1d00c75ecc Remove nia from loadstore and multiply 
Neither unit needs the NIA, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 21:42:37 +10:00
Anton Blanchard
8b88e26ece Merge pull request #43 from mikey/trivial 
Remove FIXME comment
 2019-09-11 21:42:00 +10:00
Michael Neuling
1e1b799382 Remove FIXME comment 
This was mistakenly left behind in 4d5abfb430 ("Remove dynamic
ranges from code")

Signed-off-by: Michael Neuling <mikey@neuling.org>
 2019-09-11 16:51:02 +10:00
Anton Blanchard
ff1455dea6 Merge pull request #41 from mikey/travis 
Allow a full make check on Travis
 2019-09-11 16:05:05 +10:00
Anton Blanchard
2f3ca35a6e Merge pull request #42 from antonblanchard/fetch-rework-v2 
Fetch rework
 2019-09-11 16:04:10 +10:00
Anton Blanchard
4528ef2b43 Reformat core.vhdl 2019-09-11 13:23:45 +10:00
Anton Blanchard
a2df2a10a2 Remove sim console 
We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
68533c4cfb Reduce multiply to 2 cycles 
We want all non load/store ops to take 2 cycles to make
tracking write back easier.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
9fe8d211eb Register outputs on writeback 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
c7aa683ba8 Register outputs on execute2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
819f820090 Register outputs on loadstore1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
a8f8c54b77 Move debug execute output into decode2 
This covers all units, and we avoid double printing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00
Anton Blanchard
92a7152370 Rework pipeline, add stall and flush signals 
This adds stall and flush signals to the pipeline.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-11 13:23:45 +10:00