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Author SHA1 Message Date
Paul Mackerras
a01ffaeb64 Speed up the divider a little 
This looks for cases where the next 8 bits of the quotient are obviously
going to be zero, because the top 72 bits of the 128-bit dividend
register are all zero.  In those cases we shift 8 zero bits into the
quotient and increase count by 8.  We only do this if count < 56.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2019-09-23 14:39:50 +10:00
Paul Mackerras
d5bc6c8824 Add a divider unit and a testbench for it 
This adds a divider unit, connected to the core in much the same way
that the multiplier unit is connected.  The division algorithm is
very simple-minded, taking 64 clock cycles for any division (even
32-bit division instructions).

The decoding is simplified by making use of regularities in the
instruction encoding for div* and mod* instructions.  Instead of
having PPC_* encodings from the first-stage decoder for each of the
different div* and mod* instructions, we now just have PPC_DIV and
PPC_MOD, and the inputs to the divider that indicate what sort of
division operation to do are derived from instruction word bits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
 2019-09-23 14:31:53 +10:00
Anton Blanchard
6571b13308 Merge pull request #66 from antonblanchard/reformat-4 
More reformatting
 2019-09-19 22:49:41 +10:00
Anton Blanchard
7e7010c304 Reformat crhelpers, and remove some stale code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:53:27 +10:00
Anton Blanchard
ae42370d24 Reformat helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:53:09 +10:00
Anton Blanchard
9ff86a62f5 Reformat insn_helpers 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:52:07 +10:00
Anton Blanchard
c5d327cebf Merge pull request #65 from antonblanchard/loadstore-opt 
A small loadstore optimisation, and some reformatting
 2019-09-19 21:48:22 +10:00
Anton Blanchard
687051ecbb Reformat loadstore1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:37:43 +10:00
Anton Blanchard
6e442e07a5 Reformat loadstore2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:36:51 +10:00
Anton Blanchard
e1a71e4545 loads don't do both byte reversal and sign extension 
Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 21:31:34 +10:00
Anton Blanchard
4df05e0598 Merge pull request #64 from antonblanchard/reformat-3 
Reformat some more files
 2019-09-19 21:07:31 +10:00
Anton Blanchard
48f4dcece8 Merge pull request #63 from antonblanchard/multiply-cleanup 
Multiply cleanup
 2019-09-19 20:36:26 +10:00
Anton Blanchard
df1165bdfc Reformat wishbone code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:35:42 +10:00
Anton Blanchard
06392e7eaa Reformat glibc_random 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:33:58 +10:00
Anton Blanchard
1d5e8c2eb4 Reformat simple_ram_behavioural 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:32:07 +10:00
Anton Blanchard
fd9e971b2c Reformat sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:28:37 +10:00
Anton Blanchard
28e6d343dc Reformat multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:26:55 +10:00
Anton Blanchard
fc10935797 Reformat execute2 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:24:29 +10:00
Anton Blanchard
4d0afa3a6d Reformat CR file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:22:36 +10:00
Anton Blanchard
4d9b2a1165 Reformat register file 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:21:58 +10:00
Anton Blanchard
8dd97fbe7f Reformat multiply code 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:19:46 +10:00
Anton Blanchard
99dd4de54e Don't use VHDL 2008 condition operator in multiply 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-19 20:18:01 +10:00
Anton Blanchard
550b2b8608 Merge pull request #62 from antonblanchard/byte-reverse-store-opt 
Move byte reversal of stores to first cycle
 2019-09-16 13:17:37 +10:00
Anton Blanchard
135805d2ac Merge pull request #61 from antonblanchard/execute-cleanup 
execute1 no longer needs sim_console
 2019-09-16 13:14:25 +10:00
Anton Blanchard
a061924a78 Move byte reversal of stores to first cycle 
We are seeing some timing issues with the second cycle of loadstore,
and  we aren't doing much in the first cycle, so move it here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:49:44 +10:00
Anton Blanchard
6d85920068 execute1 no longer needs sim_console 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-16 11:18:53 +10:00
Anton Blanchard
a4c8dd860a Merge pull request #60 from antonblanchard/testbenches 
Add a few more test benches
 2019-09-15 22:52:14 +10:00
Anton Blanchard
1b6eef2a5d Fix multiply_tb 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:44:01 +10:00
Anton Blanchard
1e3e16e500 Add an icache testbench 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 22:13:21 +10:00
Anton Blanchard
d573748da0 Merge pull request #56 from antonblanchard/writeback-fix3 
Remove cycle in writeback
 2019-09-15 22:08:57 +10:00
Anton Blanchard
152261fac8 Remove cycle in writeback 
The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:47:59 +10:00
Anton Blanchard
7bb88d5321 Merge pull request #59 from antonblanchard/trap-decode 
Fix make check
 2019-09-15 21:37:47 +10:00
Anton Blanchard
f5a5b91736 Merge pull request #58 from antonblanchard/decode2-assert 
Fix spurious outstanding assert
 2019-09-15 21:30:30 +10:00
Anton Blanchard
427effdaa9 Fix make check 
We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.

All these trap instructions need to be resolved at completion, not
in execute.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 21:21:36 +10:00
Anton Blanchard
d813ffb748 Fix spurious outstanding assert 
Check it in the sequential process, not the combinatorial one.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:59:24 +10:00
Anton Blanchard
30aa16d8f3 Merge pull request #57 from antonblanchard/add-nop 
Add a decode for the nop instruction
 2019-09-15 18:34:27 +10:00
Anton Blanchard
9867fb6149 Add a decode for the nop instruction 
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 18:18:24 +10:00
Anton Blanchard
85062793b1 Merge pull request #55 from antonblanchard/fetch-fix 
Add a default value for RESET_ADDRESS
 2019-09-15 11:18:42 +10:00
Anton Blanchard
d52046104f Add a default value for RESET_ADDRESS 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 10:38:49 +10:00
Anton Blanchard
71e45a82ee Merge pull request #51 from antonblanchard/writeback-fix 
Some writeback updates
 2019-09-15 09:55:10 +10:00
Anton Blanchard
e69e79d8af Reformat writeback.vhdl 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:07:34 +10:00
Anton Blanchard
50a361a5dc Exit if we try to write more than one GPR or CR in a cycle 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-15 09:04:47 +10:00
Anton Blanchard
ab34c48392 Merge pull request #50 from antonblanchard/decode1-opt 
No need to gate nia or insn in decode1
 2019-09-12 21:15:24 +10:00
Anton Blanchard
acdb2ea157 No need to gate nia or insn in decode1 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 17:06:09 +10:00
Anton Blanchard
0e6861e5db Merge pull request #49 from antonblanchard/icache-2 
Add a simple direct mapped icache
 2019-09-12 16:14:28 +10:00
Anton Blanchard
89849a6856 Add a simple direct mapped icache 
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 15:57:00 +10:00
Anton Blanchard
6cbf456388 SOC memory wishbone should clear ACK regardless of STB 
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 15:57:00 +10:00
Anton Blanchard
67446709ca Merge pull request #48 from antonblanchard/clk_gen_bypass 
Fix clk_gen_bypass
 2019-09-12 13:03:33 +10:00
Anton Blanchard
d89a9929fd Fix clk_gen_bypass 
I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2019-09-12 12:25:18 +10:00
Anton Blanchard
80aa781454 Merge pull request #47 from antonblanchard/if-fix 
Explicitly check against '1' in if statements
 2019-09-12 09:46:22 +10:00