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127 Commits 4 Branches 20 Tags
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Commit Graph

15 Commits

Author SHA1 Message Date
Andrew Kay
a137b00b0d Update pin assignments for new development board 2020-08-24 08:28:20 -05:00
Andrew Kay
28fc1c0cef Add distortion 2020-07-09 07:50:24 -05:00
Andrew Kay
411cd847dc Integrate coax_tx into top 2020-07-08 19:58:23 -05:00
Andrew Kay
e2974b2365 Implement read 2020-07-05 18:56:36 -05:00
Andrew Kay
c155c23d5f Add data bus 2020-07-05 16:43:39 -05:00
Andrew Kay
c49a82f588 First hardware test of coax_rx, increase clk frequency 2020-07-05 16:13:36 -05:00
Andrew Kay
d3ca7a1d45 testing rx_coax_bit_timer on TinyFPGA 2020-06-21 18:52:21 -05:00
Andrew Kay
0785407a49 Add TX to top 2020-03-13 21:26:13 -05:00
Andrew Kay
b750c9e756 Drop shims, for now 2020-03-03 19:52:56 -06:00
Andrew Kay
891390cb84 Attempt DP8340 and DP8341 shims 2020-02-21 20:43:52 -06:00
Andrew Kay
811a048685 Initial attempt at receiver 2020-02-17 20:47:46 -06:00
Andrew Kay
13eb0f52bd Adding tx_inverted and updating pins 2020-02-10 22:26:39 -06:00
Andrew Kay
7a78447c6c Cleanup clocks 2020-02-09 09:50:40 -06:00
Andrew Kay
9faae78fd8 Quiesce pattern 2020-02-08 18:55:11 -06:00
Andrew Kay
ad7ba12d2c Verilog templating 2020-02-04 22:11:14 -06:00