53 Commits

Author	SHA1	Message	Date
Olof Kindgren	1248043a39	Separate state and decode from CSR signals	2019-09-14 22:18:03 +02:00
Olof Kindgren	ef3fc9274d	Rename misleading signal names	2019-09-13 23:30:46 +02:00
Olof Kindgren	8c63a1a22f	Simplify bufreg.i_clr	2019-09-13 23:30:46 +02:00
Olof Kindgren	8dc137fb07	Kill of mem_init and mem_en	2019-09-13 23:30:46 +02:00
Olof Kindgren	e20e0eef8f	Optimize dbus_cyc	2019-09-13 23:30:46 +02:00
Olof Kindgren	a0ba84096a	Simplify csr stuff	2019-09-13 23:30:46 +02:00
Olof Kindgren	7425128dd8	Pass imm offsets through bufreg	2019-09-13 23:30:46 +02:00
Olof Kindgren	28a2bbdb60	Rename misleading signal name	2019-09-13 23:30:46 +02:00
Olof Kindgren	286a07bfc8	Mask rvfi_valid during reset release	2019-09-13 23:30:45 +02:00
Olof Kindgren	d2cf7e547a	Interrupt refactoring	2019-08-25 22:47:29 +02:00
Olof Kindgren	3c1582b7b2	Remove unused RVFI defines	2019-08-14 22:15:45 +02:00
Olof Kindgren	892388627c	Speed up memory accesses	2019-08-14 22:15:45 +02:00
Olof Kindgren	31852f175d	Simplify alu_cmp_eq control logic	2019-07-23 12:10:38 +02:00
Olof Kindgren	af3b82f9ac	Optimize take_branch condition	2019-07-23 12:10:38 +02:00
Olof Kindgren	16c93a58ee	Move mepc and mtval into RF memory	2019-07-08 07:49:58 +02:00
AlAlves	2fb56ac62d	Update serv_top.v	2019-07-08 07:47:12 +02:00
Olof Kindgren	e107627e71	Reduce warnings	2019-06-24 15:22:08 +02:00
Olof Kindgren	42ac1e5e4d	Store CSR in RF RAM ... Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.	2019-06-07 19:39:18 +02:00
Olof Kindgren	b0a062ae21	Speed up instruction fetching	2019-04-12 08:15:08 +02:00
Olof Kindgren	a550137453	Use bufreg for shifter	2019-03-20 08:35:43 +01:00
Olof Kindgren	fe33d6abdc	Move dbus address handling to global bufreg	2019-01-15 08:00:32 +01:00
Olof Kindgren	9a97c535bd	Use ring buffer for counter LSBs	2019-01-15 08:00:32 +01:00
Olof Kindgren	45f6d408f8	Remove dead code	2019-01-15 08:00:32 +01:00
Olof Kindgren	3a68cc0e77	Improve critical path in ctrl	2019-01-15 08:00:32 +01:00
Olof Kindgren	813f9f4951	Rewrite CSR selection	2019-01-10 18:15:20 +01:00
Olof Kindgren	e3e616903e	Optimize bool operations	2018-12-25 13:13:04 +01:00
Olof Kindgren	4a224fc985	Fix failing compliance tests	2018-12-13 12:03:42 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	af1d4da8bf	Fix rvfi logic	2018-12-11 22:02:03 +01:00
Olof Kindgren	6cd3d2d3ef	Fix rvfi_insn	2018-12-06 23:47:52 +01:00
Olof Kindgren	cd983190b3	Interrupts working. Adding philosophers example	2018-11-26 23:03:40 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	e1f5bcc4f3	Rewrite register file	2018-11-26 00:09:52 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	7666ac4092	synthesized netlist works	2018-11-18 13:05:38 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	0036756157	Pass compliance tests	2018-11-15 14:16:01 +01:00
Olof Kindgren	34fc93ba09	Fix misaligned jumps	2018-11-15 12:50:40 +01:00
Olof Kindgren	f12f8ecf61	Remove MEM_WAIT state	2018-11-15 09:59:25 +01:00
Olof Kindgren	aa0e3aa77e	Handle misaligned jal	2018-11-15 08:49:29 +01:00
Olof Kindgren	a92c933af1	csr, verilator, traps	2018-11-14 12:16:20 +01:00
Olof Kindgren	3c98d35766	Change to wb interface	2018-11-09 21:26:13 +01:00
Olof Kindgren	cbbdaed112	slli, srli, add, sll, sltiu, slt, xor, srl, sra, or, and	2018-11-02 13:48:08 +01:00
Olof Kindgren	c90920d9b2	bge, bltu, bgeu	2018-11-01 09:35:49 +01:00
Olof Kindgren	d4bbe17e78	jalr, blt	2018-10-31 14:51:28 +01:00
Olof Kindgren	d4b2697761	auipc, sub	2018-10-30 23:33:28 +01:00
Olof Kindgren	96b1906676	bne, srai	2018-10-30 22:41:05 +01:00