Miodrag Milanovic
bf1802bfee
Rename some of bels
2025-06-30 12:38:51 +02:00
Lofty
21e1e7b269
comment the relevant CPE inputs in check_multipliers
2025-06-30 11:33:44 +01:00
Lofty
5940aba7d6
explicitly zero some params in B passthrough
2025-06-30 11:07:51 +01:00
Lofty
b5ad325546
multiplier support from lofty/gatemate-mult
2025-06-30 10:43:09 +01:00
Miodrag Milanovic
e03e80c0e1
Fixed warning
2025-06-30 11:28:18 +02:00
Miodrag Milanovic
628e266e30
Add more timings models, need updated values
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
2dc2732225
Make CPE_LATCH separate
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
474ba2d1e7
Fix clang compile error
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
b150f24e85
Fix signal routing
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
4a92942acb
Make code more c++ compliant
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
04cbf65074
Resolve name conflicts
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
6b46e9fe8a
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
847ea16a22
Bump required version of database
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
2db8aa1e8a
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
31bceb02e9
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
025af8b6d2
clangformat
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e963ac28bb
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
c0e1f45dc0
Optimize
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
8d3e43d89f
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
65678b876e
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
aeb0ba4e54
Cleanups
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
316ebbf26b
Cleanup
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9f9b5f0e8f
Cleanups
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
23ca3cd2b3
Small fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
96b029d560
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9bf85f6e37
Use CP_OUT for adders
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
6cfccc502f
Fix GUI
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
f57c9f4cb7
Renamed some timings
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9de539cd95
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
d5bde28a7c
Add dummy L2T4
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
5cf5ad9c64
Fix ramio
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
271c9f5b97
Use L2T4 for constant drivers
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
b75b0cc562
Fix ADDF
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
fb4f63f8c2
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
6f8d1f2dba
Fixes for ram_o
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
9f1d9d3577
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e32f3a3792
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
d974683ffb
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
3eda1edec8
Fixes
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
e1cc5d06cb
Start using FFs
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
bee4aa0e55
CPE mapping improvements
2025-06-30 11:22:44 +02:00
Miodrag Milanovic
bf7eb65dea
Add lut tree tests for future improvements
2025-06-30 11:22:44 +02:00
YRabbit
39f020b033
Gowin. Unbreak the segment routing. ( #1508 )
...
Use loop enumeration of PIPs instead of direct name construction for the
upper and lower ends of the segment wire.
Also do not allow clock wires for segments.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou >
2025-06-30 10:14:21 +02:00
Lofty
e642e21f9b
himbaechel: output normalised wire in getWireByName ( #1506 )
2025-06-25 18:46:19 +02:00
gatecat
9ade2d1877
himbaechel: Add Python binding for get_tile_wire_range
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 18:37:17 +02:00
gatecat
1cd1e4a8d9
xilinx: Fix packing of weird mux trees
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 12:38:11 +02:00
gatecat
23cf1d3b92
docs: Fix outdated content in generic.md
...
Fixes #1263
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 12:02:27 +02:00
gatecat
ff695f26d5
sdc: Fix EOF handling during string parse
...
Fixes #1490
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:58:11 +02:00
gatecat
f74aee7047
gowin: Remove logspam during build
...
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:49:45 +02:00
gatecat
a77eb9e941
ice40: Fix accidental division by DIVR in 2_PAD mode
...
Fixes #1500
Signed-off-by: gatecat <gatecat@ds0.me >
2025-06-25 11:44:16 +02:00