Emil J. Tywoniak
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c6923ed2a7
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ffmerge: initvals signorm compatibility fixup
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2026-03-26 23:53:53 +01:00 |
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Emil J. Tywoniak
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c06755f1bb
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timinginfo: special-case $specify2 in signorm invariant
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2026-03-26 19:42:33 +01:00 |
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Emil J. Tywoniak
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d33d048874
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fixup! opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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2026-03-25 12:39:33 +01:00 |
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Emil J. Tywoniak
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e3edd1501e
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modtools: fix port_del db erase
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2026-03-25 12:17:23 +01:00 |
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Emil J. Tywoniak
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1775bce173
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opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped
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2026-03-25 11:50:17 +01:00 |
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Emil J. Tywoniak
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c416d39ebb
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techmap: read_verilog -icells, I mean, obviously
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2026-03-24 23:25:42 +01:00 |
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Emil J. Tywoniak
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09040adb2c
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connect: remove input ports on conflict
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2026-03-24 23:23:27 +01:00 |
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Emil J. Tywoniak
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15665773fd
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opt_dff: sigma harder, FfDataSigMapped
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2026-03-24 23:22:39 +01:00 |
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Emil J. Tywoniak
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1fb904e281
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ff: add FfDataSigMapped
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2026-03-24 23:22:39 +01:00 |
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Emil J. Tywoniak
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734249a5e6
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opt_dff: temporarily disable signorm due to muxtree traversal
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2026-03-24 23:22:39 +01:00 |
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Emil J. Tywoniak
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49d08591e3
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tests: fix rtlil roundtrip test
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2026-03-24 23:22:39 +01:00 |
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Emil J. Tywoniak
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872c940259
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design: fix signorm commit connectivity to design
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2026-03-18 00:44:20 +01:00 |
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Emil J. Tywoniak
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a4398d4d90
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fixup! cxxrtl: ignore $input_port
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2026-03-17 23:00:22 +01:00 |
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Emil J. Tywoniak
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b97a8cdfe3
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cxxrtl: ignore $input_port
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2026-03-17 18:06:07 +01:00 |
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Emil J. Tywoniak
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55189bc65c
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flatten: redo signormalization to work around fanout issue
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2026-03-17 18:04:41 +01:00 |
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Emil J. Tywoniak
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4c8b7818f4
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abstract: fix test signorm
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2026-03-17 17:39:05 +01:00 |
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Emil J. Tywoniak
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c01d88c303
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signorm: disable passes that use rewrite_sigspecs
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2026-03-17 17:35:57 +01:00 |
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Emil J. Tywoniak
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961c9a90d6
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aiger: ignore $input_port
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2026-03-17 17:32:56 +01:00 |
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Emil J. Tywoniak
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c5d4b435bd
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check: stitch info about $connect ports together for driver analysis
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2026-03-17 17:29:23 +01:00 |
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Emil J. Tywoniak
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bbf5b3c738
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signorm: remove $input cells when leaving
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2026-03-17 16:37:00 +01:00 |
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Emil J. Tywoniak
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3257b8ae1e
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abstract: skip $input_port cells
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2026-03-17 16:34:41 +01:00 |
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Emil J. Tywoniak
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9d3928c014
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flatten: skip $input_port cells in template module
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2026-03-17 16:11:32 +01:00 |
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Emil J. Tywoniak
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debc2c3977
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signorm: skip const when fixing fanout
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2026-03-17 11:28:10 +01:00 |
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Emil J. Tywoniak
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869a7303b0
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signorm: disable in passes that use swap_names
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2026-03-16 22:45:29 +01:00 |
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Emil J. Tywoniak
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3502a51598
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opt_expr: fix invert_map
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2026-03-13 12:18:48 +01:00 |
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Emil J. Tywoniak
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aee094e3c4
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fixup! fixup! satgen: support $connect
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2026-03-12 22:53:31 +01:00 |
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Emil J. Tywoniak
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4d1f8fd7d3
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fixup! satgen: support $connect
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2026-03-12 22:16:06 +01:00 |
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Emil J. Tywoniak
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0d353591fe
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satgen: support $connect
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2026-03-12 22:15:34 +01:00 |
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Emil J. Tywoniak
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ae946a598c
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rtlil: add dump_sigmap for hacky signorm debugging
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2026-03-12 22:13:21 +01:00 |
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Emil J. Tywoniak
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e7a97360a8
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techmap: disable signorm more
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2026-03-12 22:11:06 +01:00 |
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Emil J. Tywoniak
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04311e3e53
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techmap: disable signorm
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2026-03-11 21:30:27 +01:00 |
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Emil J. Tywoniak
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8bad1a2035
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opt_hier: disable signorm
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2026-03-11 21:26:12 +01:00 |
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Emil J. Tywoniak
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4611e90533
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timinginfo: disable output wire check due to signorm
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2026-03-11 21:25:00 +01:00 |
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Emil J. Tywoniak
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44917f50d9
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rtlil: forbid rewrite_sigspecs in signorm
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2026-03-11 21:07:06 +01:00 |
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Emil J. Tywoniak
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d39ce10601
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opt_merge_inc: re add initvals deletion
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2026-03-11 12:35:16 +01:00 |
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Emil J. Tywoniak
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621bb778f5
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synth_ice40: always read abc9 model to understand port direction
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2026-03-11 12:25:37 +01:00 |
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Emil J. Tywoniak
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4c90e26298
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tests: adjust to input_port and init behavior (sketchy)
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2026-03-10 14:09:31 +01:00 |
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Emil J. Tywoniak
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30ac7d271c
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satgen: cover $input_port
(cherry picked from commit d199195785)
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2026-03-10 14:06:45 +01:00 |
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Emil J. Tywoniak
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c3433bced7
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tests: adjust to input_port and init behavior (sketchy)
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2026-03-10 14:05:37 +01:00 |
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Emil J. Tywoniak
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45a254cf61
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tests: adjust to input_port and init behavior (sketchy)
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2026-03-10 14:02:46 +01:00 |
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Emil J. Tywoniak
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8375f11fa5
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wreduce: fixup initvals after setPort
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2026-03-10 14:01:57 +01:00 |
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Emil J. Tywoniak
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298b755fb7
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modtools: fix database sanity on wire name swap
(cherry picked from commit c75d80905a)
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2026-03-09 23:46:53 +01:00 |
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Emil J. Tywoniak
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58ba984498
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ff: fixup initvals with signorm direct drive wire if it's created, not old driven wire
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2026-03-09 23:38:10 +01:00 |
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Emil J. Tywoniak
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25edde1c3c
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tests: adjust to input_port and init behavior (sketchy)
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2026-03-09 21:21:45 +01:00 |
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Emil J. Tywoniak
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d2bc970ef9
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rtlil: fix zero width SigSpec crash in signorm setPort unsetPort
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2026-03-09 21:20:23 +01:00 |
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Emil J. Tywoniak
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bdce610f3d
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bug2920: disable
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2026-03-09 16:37:30 +01:00 |
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Emil J. Tywoniak
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b206223c40
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rtlil_bufnorm: fix cell deletion deferral bug
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2026-03-07 01:10:04 +01:00 |
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Emil J. Tywoniak
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b7c97ba743
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tests: adjust to input_port and init behavior (sketchy)
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2026-03-07 01:08:57 +01:00 |
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Emil J. Tywoniak
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7c5128a08a
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check: don't fail on $input_port
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2026-03-07 00:42:01 +01:00 |
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Emil J. Tywoniak
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c6b9f5d8ff
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mem: fix signorm cell type morph
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2026-03-07 00:41:24 +01:00 |
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