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Author	SHA1	Message	Date
J	e14eca18c0	CPU comes up. Lattice SPR works. LCD works.	2019-03-30 17:21:02 -04:00
J	07025535a6	merge	2019-03-30 00:14:00 -04:00
J	cc164bb8b6	Link order matters? Yes, yes it does...	2019-03-30 00:12:12 -04:00
J	3ec7c27f36	Continue simple cleanups of pinouts and platform split. Still doesn't work, though	2019-03-27 21:04:53 -04:00
J	4d896e726c	Minor change to pinouts for v1.1 board	2019-03-26 12:05:44 -04:00
J	d21f78598e	With Lattice SPR memory, and memory test. Doesn't synth correctly, sim is correct.	2019-03-25 21:50:49 -04:00
J	520a01319c	Free42 / up5k top level sim driver script	2019-03-19 16:45:37 -04:00
J	f7ad4be38a	Finish Free42 pinout. First synth with all pins. Seems to break LCD?	2019-03-19 16:44:01 -04:00
J	bcd796f196	Add pinout constraints for 42s	2019-03-18 17:41:13 -04:00
J	07afa61fa1	Drives LCD with ASCII renderer. Split main.c off for 42s	2019-03-18 17:39:56 -04:00
J	2246a52244	Work around strange %pr bug in entry.c. Finally runs to C code	2019-03-17 17:03:19 -04:00
J	d6d809c516	Attempt to avoid write conflict on Lattice EB RAM	2019-03-15 16:46:15 -04:00
J	beada4032f	Add simulation stuff for register file	2019-03-14 22:56:02 -04:00
J	2f0f7d2797	A few warnings fixed	2019-03-13 19:40:04 -04:00
J	c611736bad	Sync RAM register file implemntation	2019-03-13 17:05:56 -04:00
J	fb8fdd41c7	move back to ghdl because nvc can't trace records yet, even though it simulates them	2019-03-12 22:42:41 -04:00
J	93d011ba48	Add sim by default and wave viewer ctl file for reg file debug	2019-03-08 01:37:20 -05:00
J	d94eb15232	Actually add sim model for Lattice HF clk	2019-03-08 01:10:20 -05:00
J	dfd7c38c98	Change from UP5k EVB to updino v2.0. Add sim model for Lattice HF clk	2019-03-08 01:09:52 -05:00
J	480c4cefe0	Pin mapping for EVB	2019-03-05 22:55:59 -05:00
J	f0dbd0a33e	correct outputs for Lattice EVB. Fix stack location. Still crashes with result code 0x11 on the LEDs	2019-03-05 02:17:06 -05:00
J	b1176ec9aa	First synthesys for ICE40 UP5k with everything to blink LEDs	2019-03-04 01:17:33 -05:00
J	4a6746a0b1	With single port RAM	2019-03-03 23:16:35 -05:00
J	a0acbcafdc	Add testrom, modified for small memory... enable tests if you need in Makefile	2019-03-03 20:55:24 -05:00
J	9e5f83edd9	Add in the test rom	2019-03-03 19:35:20 -05:00
J	ea1dd551f9	Work around bugs in Lattice / Synplicity VHDL toolchain. Namespace bugs. FIXME: Better names need to be used	2019-03-03 17:29:03 -05:00
J	f35876f9bf	Regfile now uses sync ram, -ve clock read. Generics have defaults	2019-03-03 16:28:34 -05:00
J	eaad427655	Import from the git version found in work/nickg on my trash can mac	2019-03-03 14:48:57 -05:00