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Author SHA1 Message Date
Olof Kindgren
bad823ff6d Fix syntax error for o_take_branch 2019-09-26 22:59:46 +02:00
Olof Kindgren
ca2beaf786 Pass rf_rreq through serv_state 2019-09-26 22:59:46 +02:00
Olof Kindgren
3d6eb3feca Separate rf_ready and dbus_ack 2019-09-26 22:59:46 +02:00
Florian Zaruba
27621a285e rtl: Make compatible to Synopsys Design Compiler 
Synopysis DC has problems with forward references and initial
statements. Fixed that for better compatibility.
 2019-09-26 22:57:40 +02:00
Olof Kindgren
ec6c7a7cd5 Update README 2019-09-16 16:57:56 +02:00
Olof Kindgren
920ad92bc7 Remove unused rs_en signal 2019-09-16 10:45:42 +02:00
Olof Kindgren
6518b5f30f Simplify bufreg_hold 2019-09-16 09:05:47 +02:00
Olof Kindgren
ef7706f26b Simplify two-stage signalling 2019-09-16 09:03:02 +02:00
Olof Kindgren
d4c782bce6 Set o_dbus_we directly from decode 2019-09-16 00:13:21 +02:00
Olof Kindgren
b9e410a0a0 Remove bytepos from serv_mem_if 2019-09-16 00:07:58 +02:00
Olof Kindgren
5a44634ee5 Avoid exposing funct3 from decode 2019-09-15 23:50:02 +02:00
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
7289a68f6e Separate state from o_bufreg_loop 2019-09-14 22:52:41 +02:00
Olof Kindgren
c0a177aebe Simplify o_alu_cmp_uns 2019-09-14 22:21:25 +02:00
Olof Kindgren
1248043a39 Separate state and decode from CSR signals 2019-09-14 22:18:03 +02:00
Olof Kindgren
ef3fc9274d Rename misleading signal names 2019-09-13 23:30:46 +02:00
Olof Kindgren
8c63a1a22f Simplify bufreg.i_clr 2019-09-13 23:30:46 +02:00
Olof Kindgren
8dc137fb07 Kill of mem_init and mem_en 2019-09-13 23:30:46 +02:00
Olof Kindgren
e20e0eef8f Optimize dbus_cyc 2019-09-13 23:30:46 +02:00
Olof Kindgren
8cd9742b53 Use two write ports for RF/CSR RAM 2019-09-13 23:30:46 +02:00
Olof Kindgren
a0ba84096a Simplify csr stuff 2019-09-13 23:30:46 +02:00
Olof Kindgren
7425128dd8 Pass imm offsets through bufreg 2019-09-13 23:30:46 +02:00
Olof Kindgren
28a2bbdb60 Rename misleading signal name 2019-09-13 23:30:46 +02:00
Olof Kindgren
286a07bfc8 Mask rvfi_valid during reset release 2019-09-13 23:30:45 +02:00
Olof Kindgren
e059b7cf09 Add timeout argument 2019-08-25 22:52:34 +02:00
Olof Kindgren
65eb89323a Replace wb_ram with servant_ram 2019-08-25 22:51:50 +02:00
Olof Kindgren
d2cf7e547a Interrupt refactoring 2019-08-25 22:47:29 +02:00
Olof Kindgren
3c1582b7b2 Remove unused RVFI defines 2019-08-14 22:15:45 +02:00
Olof Kindgren
892388627c Speed up memory accesses 2019-08-14 22:15:45 +02:00
Olof Kindgren
f754fffdac Make default target runnable 2019-07-29 08:41:03 +02:00
Olof Kindgren
71a1abe602 Add missing RVFI port 2019-07-23 13:03:12 +02:00
Olof Kindgren
fb7c6c1458 Simplify csr_en logic 2019-07-23 12:10:38 +02:00
Olof Kindgren
31852f175d Simplify alu_cmp_eq control logic 2019-07-23 12:10:38 +02:00
Olof Kindgren
af3b82f9ac Optimize take_branch condition 2019-07-23 12:10:38 +02:00
Olof Kindgren
88b199a97c Fix typo in service reset signal 2019-07-22 22:56:27 +02:00
Olof Kindgren
16c93a58ee Move mepc and mtval into RF memory 2019-07-08 07:49:58 +02:00
Olof Kindgren
93f7b582bb Remove unused localparam 2019-07-08 07:47:45 +02:00
AlAlves
2fb56ac62d Update serv_top.v 2019-07-08 07:47:12 +02:00
Olof Kindgren
e107627e71 Reduce warnings 2019-06-24 15:22:08 +02:00
Olof Kindgren
4b371c533f Add nexys a7 support 2019-06-24 13:18:34 +02:00
Olof Kindgren
fe9d2677ba Add SERV_CLEAR_RAM parameter 2019-06-24 13:18:34 +02:00
Olof Kindgren
70bdce9d8e Refactor gpio/uart output in tb 2019-06-24 13:18:34 +02:00
Olof Kindgren
bad78b0bd7 Declare wires before use 2019-06-24 13:18:34 +02:00
Olof Kindgren
cf7e516526 Refactor to separate serv and servant 2019-06-24 13:18:34 +02:00
Aliaksei Chapyzhenka
c91a5a43c1 Update README.md 2019-06-07 23:27:51 +02:00
Olof Kindgren
42ac1e5e4d Store CSR in RF RAM 
Since FPGA uses fixed-size RAM, it's better in most cases to store
the CSR in unused memory positions in that RAM.

Since the decoding is made more complex, the old register file
implementation is kept around since that is more efficient when we
don't want CSR and potentially when the FPGA support hardware
shift registers.
 2019-06-07 19:39:18 +02:00
Olof Kindgren
b0a062ae21 Speed up instruction fetching 2019-04-12 08:15:08 +02:00
Olof Kindgren
bba836ad8c Fix width mismatches to make code verilator clean 2019-03-25 20:57:13 +01:00
Olof Kindgren
3438e0f172 Optimize mcause CSR 2019-03-21 09:24:11 +01:00
Olof Kindgren
6e91409990 Optimize alu eq check 2019-03-20 08:35:43 +01:00