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mirror of synced 2026-01-18 16:57:00 +00:00

246 Commits

Author SHA1 Message Date
Romain Dolbeau
56586bcdf1 upd readme 2021-11-20 08:38:37 +01:00
Romain Dolbeau
429697db18 minor details, more non-working intr code 2021-11-20 08:38:03 +01:00
Romain Dolbeau
802d8118c5 better sd(ram|card) drivers 2021-11-19 21:27:38 +01:00
Romain Dolbeau
c9fbaf61f8 various updates, and prom driver for sdcard 2021-11-17 19:19:32 +01:00
Romain Dolbeau
a3d210b27f can't get async (interrupt-based) sdram driver to work 2021-11-14 15:28:40 +01:00
Romain Dolbeau
a944704ef4 sdcard, interrupt line on sdram 2021-11-13 12:42:18 +01:00
Romain Dolbeau
94c36e7a36 fb stuff 2021-11-13 12:41:37 +01:00
Romain Dolbeau
42f39c846f drop V1.0 2021-11-13 12:41:05 +01:00
Romain Dolbeau
334759951b cleanup, preliminary sdcard driver 2021-11-13 12:40:34 +01:00
Romain Dolbeau
893e5a7c67 Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-11-13 12:05:05 +01:00
Romain Dolbeau
f6b7dcaba3 upd backplate 2021-11-13 12:04:26 +01:00
Romain Dolbeau
3af873fdb7 add remove functions, doesn't help 2021-11-07 08:52:56 +01:00
Romain Dolbeau
98ba64beda cleanup 2021-11-07 08:52:16 +01:00
Romain Dolbeau
479c780b27 cleanup 2021-11-06 10:21:59 +01:00
Romain Dolbeau
87687de1ea comment 2021-11-06 10:19:07 +01:00
Romain Dolbeau
3c96a56dfb fix checksum-less building 2021-11-06 10:18:23 +01:00
Romain Dolbeau
ef9d16507b use fth cst 2021-11-06 10:18:02 +01:00
Romain Dolbeau
35dee425e9 typo fix 2021-11-06 10:17:51 +01:00
Romain Dolbeau
d7d1772a48 Add sext.b to Vex, as some are generated in -O2/-O3 (none in -Os) 2021-11-01 15:23:27 +01:00
Romain Dolbeau
671953941f Add FSR to Vex, use it for unaligned blits 2021-11-01 14:34:34 +01:00
Romain Dolbeau
97f688dd7d Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-10-31 19:59:07 +01:00
Romain Dolbeau
2cda6c49d6 minor changes 2021-10-31 19:58:19 +01:00
Romain Dolbeau
c20d1f321f smaller vex 2021-10-31 19:57:39 +01:00
Romain Dolbeau
afdfe4a686 support more Po2 FB sizes 2021-10-30 12:51:02 +02:00
Romain Dolbeau
6f04a9bd73 more configuratble blit rom 2021-10-30 11:53:09 +02:00
Romain Dolbeau
417095d2c0 extrac cycle to meet timings at 1920x1080@60 when using HW cursor 2021-10-30 11:52:58 +02:00
Romain Dolbeau
f57a22e434 add a (working this time) Dcache to Vex 2021-10-30 11:52:01 +02:00
Romain Dolbeau
c2da8f5633 more improvements 2021-10-30 11:41:05 +02:00
Romain Dolbeau
1344a2e7e7 Font for the on-screen debug display 2021-10-30 10:04:12 +02:00
Romain Dolbeau
a85542d029 CG6 accel emulation (still slow) 2021-10-30 10:03:11 +02:00
Romain Dolbeau
f5a1067806 fix broken timeout, some (disabled, for testing) stat stuff 2021-10-30 10:02:33 +02:00
Romain Dolbeau
06bff62901 move the wishbone CDC locally ; speedgrade from part 2021-10-30 10:01:26 +02:00
Romain Dolbeau
dea62d3d73 trying to improve the timing in the vga_clk domain 2021-10-24 20:02:59 +02:00
Romain Dolbeau
fa0387fe96 trying to improve the cg accel stuff 2021-10-24 20:02:34 +02:00
Romain Dolbeau
ee1e8d3450 Dcache-less Vex 2021-10-24 20:02:02 +02:00
Romain Dolbeau
5b8124b939 proto CG6 2021-10-15 22:38:27 +02:00
Romain Dolbeau
d552b1cd52 Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-10-11 08:06:10 +02:00
Romain Dolbeau
8642dd8c40 Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-10-11 08:05:26 +02:00
Romain Dolbeau
27a310fadf one more word of warning 2021-10-11 08:05:15 +02:00
Romain Dolbeau
6c6cb87395 WB FSM was broken (cmap to be tested still) 2021-10-10 19:23:39 +02:00
Romain Dolbeau
3e95f078f5 fix irq priority handling in ohci-sbus device 2021-10-09 17:51:33 +02:00
Romain Dolbeau
232b7795cd Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-10-09 11:26:32 +02:00
Romain Dolbeau
bd992ad421 add VGA222 Pmod 2021-10-09 11:26:13 +02:00
Romain Dolbeau
e31ea588f1 don't need the extra 256 KiB 2021-10-09 11:19:47 +02:00
Romain Dolbeau
04612ea864 add a known limitation 2021-10-09 11:11:02 +02:00
Romain Dolbeau
f27c8d86f6 README in Pictures 2021-10-09 10:44:40 +02:00
Romain Dolbeau
018f271c67 pictures of V1.2 2021-10-09 10:40:38 +02:00
Romain Dolbeau
3afb728485 update README to V1.2 2021-10-09 10:39:51 +02:00
Romain Dolbeau
d417ba7206 Merge branch 'v1_2' into main 2021-10-09 10:26:03 +02:00
Romain Dolbeau
1c690cbd90 Merge branch 'main' of github.com:rdolbeau/SBusFPGA into main 2021-10-09 10:25:47 +02:00