- was more a hack than a design; inheritance stack now cleaner
- RtclRw11Unit: drop fpCpu, use added Cpu()=0 instead
- RtclRw11UnitBase: add TUV,TB; add TUV* ObjUV(); inherit from TB
- RtclRw11Unit(Disk|Stream|Tape|Term): define ObjUV();inherit from RtclRw11Unit
- RtclRw11Unit(dev): inherit from RtclRw11UnitBase
- document urjtag build (jtag in Ubuntu 16.04 is broken)
- add environment sanity wrappers for acroread,awk,firefox to ensure
proper operation of vivado under Ubuntu 16.04
- Vivado is used with -fsm_extraction one_hot. Starting with Vivado 2016.3
this triggers fsm recognition and re-coding of two gray counter modules.
This not only defeats the purpose of the gray coded counter, it also
caused some constraints to fail. Added attributes to prevent fsm extraction
- the logic of `connect_hw_server` and `get_hw_servers` changed after Vivado
2015.1. The `make <design>.vconfig` command worked up to Vivado 2016.2 due
to some recovery mechanism, and finally broke with 2016.3. Fixed the
call to `get_hw_servers`.
- pdp11_sequencer.vhd: CPUERR cleared by CRESET
- mminki.mac: added, procedure to initialize MMU, kernel I space only
- test_w11a_cpuerr.tcl: added, test cpuerr register
- added more README's
- editorial changes
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
rbus->ibus window. Replaces with a 4k word window for whole IO page.
- utilize rlink protocol version 4 features in w11a backend
- use attn notifies to dispatch attn handlers
- use larger blocks (7*512 rather 1*512 bytes) for rdma transfers
- use labo and merge csr updates with last block transfer
- this combined reduces the number of round trips by a factor 2 to 3,
and in some cases the throughput accordingly.
- Goals for rlink v4
- 16 bit addresses (instead of 8 bit)
- more robust encoding, support for error recovery at transport level
- add features to reduce round trips
- improved attention handling
- new 'list abort' command
- For further details see README_Rlink_V4.txt
- use own C++ based tcl shell tclshcpp instead of tclsh
divisor or quotient were the largest negative integer (100000 or -32768).
This is corrected now, for details see ECO-026-div.txt
- some minor updates and fixes to support scripts
- xtwi usage and XTWI_PATH setup explained in INSTALL.txt
- after 0.581: documentation updates, no functional changes
- from 0.5 -> 0.6:
- revised ibus and rbus protocol; backend server rewritten; Nexys3 port;
Cypress Fx2 support; LP11,PC11 support
- new reference system
- switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
- C++ and Tcl based backend server now fully functional, supports with
DL11, RK11, LP11 and PC11 all devices available in w11a designs
- the old perl based backend server (pi_rri) is obsolete and removed
- operating system kits reorganized
- new C++ and Tcl based backend server supports now RK11 handling
- w11a systems operate with rlink over USB on nexsy2 and nexsy3 boards.
See w11a_os_guide.txt for details
- C++ and Tcl based backend server: many support classes for interfacing to
w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler.
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
- Added simple simulation model of Cypress FX2 and test benches for
functional verifcation of FX2 controller
- Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys
- Added test systems for rlink over USB verification for Nexys3 & Atlys
- re-organized handling of board and derived clocks in test benches
- added message filter definitions for some designs (.mfset files)
- added Cypress EZ-USB FX2 controller (USB interface)
- added firmware for EZ-USB FX2 supporting jtag access and data transfer
- FPGA configure over USB now supported directly in make build flow
- added test systems for USB testing and rlink over USB verification
- no functional change of w11a CPU core or any pre-existing test systems
- Note: Carefully read the disclaimer about usage of USB VID/PID numbers
in the file README_USB-VID-PID.txt. You'll be responsible for any
misuse of the defaults provided with the project sources !!
- added xon/xoff (software flow control) support to serport library
- added test systems for serport verification
- use new serport stack in sys_w11a_* and sys_tst_rlink_* systems
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
