22 Commits

Author	SHA1	Message	Date
Andrew Kay	4fa9e0381b	Headers	2020-07-09 18:51:38 -05:00
Andrew Kay	32419dd760	Disable receiver input when not enabled	2020-07-09 17:21:30 -05:00
Andrew Kay	28fc1c0cef	Add distortion	2020-07-09 07:50:24 -05:00
Andrew Kay	411cd847dc	Integrate coax_tx into top	2020-07-08 19:58:23 -05:00
Andrew Kay	e2974b2365	Implement read	2020-07-05 18:56:36 -05:00
Andrew Kay	c155c23d5f	Add data bus	2020-07-05 16:43:39 -05:00
Andrew Kay	c49a82f588	First hardware test of coax_rx, increase clk frequency	2020-07-05 16:13:36 -05:00
Andrew Kay	d3ca7a1d45	testing rx_coax_bit_timer on TinyFPGA	2020-06-21 18:52:21 -05:00
Andrew Kay	9dd8d37ef5	wip	2020-06-16 16:53:53 -05:00
Andrew Kay	03af715ec5	Start over	2020-06-14 10:05:02 -05:00
Andrew Kay	6ca7b6ba0e	Add receiver enable	2020-03-28 18:06:20 -05:00
Andrew Kay	0785407a49	Add TX to top	2020-03-13 21:26:13 -05:00
Andrew Kay	b750c9e756	Drop shims, for now	2020-03-03 19:52:56 -06:00
Andrew Kay	891390cb84	Attempt DP8340 and DP8341 shims	2020-02-21 20:43:52 -06:00
Andrew Kay	811a048685	Initial attempt at receiver	2020-02-17 20:47:46 -06:00
Andrew Kay	d4eaeecec2	Hello world	2020-02-12 23:13:21 -06:00
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	13eb0f52bd	Adding tx_inverted and updating pins	2020-02-10 22:26:39 -06:00
Andrew Kay	7a78447c6c	Cleanup clocks	2020-02-09 09:50:40 -06:00
Andrew Kay	9faae78fd8	Quiesce pattern	2020-02-08 18:55:11 -06:00
Andrew Kay	0b618d6b35	Adding a 19 MHz clock	2020-02-08 17:43:09 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00