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Commit Graph

100 Commits

Author SHA1 Message Date
Jim
73eaf5cfd5 jump directly to shift to eliminate a sub-switch (Primos rebuild gcov)
After profiling Primos rebuild, shift instructions are #8
2007-10-21 00:00:00 -04:00
Jim
9d6903b4e2 prep devamlc for real serial, changed ints to shorts for queue instructions
changed devamlc in prep for real serial support:
- changed .sockfd to .fd
- change transmit to directly access queue, to remove select
2007-10-19 00:00:00 -04:00
Jim
1e85a5c348 fixed MAJOR BUG (since em83) where memory writes were being lost
because the "page unmodified" bit wasn't being cleared.  If Primos
needed the page, it wouldn't write it to the paging disk first.
2007-10-17 00:00:00 -04:00
Jim
3bb5eefc61 fixed multiple extension segments (stex, pcl, prtn), perf tweaks
-- this was causing the LISTENER_ORDER$ signals after DIAG
-- also was causing HELP to fail sporadically (HELP MTRESUME)
removed TB_xxx flags (identical to T_xxx)
added some eap hints
changed to pop the concealed stack earlier
changed LDLR/LDAR to load result from RP if ea is 7
changed STLR/STAR to store result in RP if ea is 7
added new trace flags for GET/PUT (unimplemented)
2007-10-16 00:00:00 -04:00
Jim
dffe43212e used gcov info to reorder some stuff in ea64v (ea64v4.h) 2007-10-12 00:00:00 -04:00
Jim
afdf6057b1 FP exceptions, -DNOREG for -O0 and -DBG compiles, perf tweaks, gcov
reworked ring/register fix so that Primos nevers sees RP faulted
  but we don't have to do extra tests in the fetch loop
changed EAxxx routines to use RP segno when EA = register
added FP exception fault to ieeepr8 and all FP routines
added round flag to ieeepr8 (though not sure it's rounding correctly)
used gcov info to reorder some stuff in ea16s, ea32s, ea32r64r
changed warn() and fatal() to use get16t; prevpc might be a register
IMPORTANT NOTE: to compile with -O0, also use -DNOREG (gcc bug)
2007-10-12 00:00:00 -04:00
Jim
36254e2fba RP ring bits weren't being preserved when executing code in registers.
This caused a HLT instruction in the register to halt the machine from ring 3
2007-10-09 00:00:00 -04:00
Jim
4779beb25e removed dup iget16 in BDX, no wait common case handled first in WAIT
cleaned up/added a few comments, added messages to fatal() calls
2007-10-06 00:00:00 -04:00
Jim
c463fce90d large changes to dispatch.h to support 2 tables +
separate R/S-mode mem ref dispatch table to avoid R-mode check in V-mode inst
2007-10-04 00:00:00 -04:00
Jim
c845fdce12 changed main loop to test inhcount only when intvec is set;
this also required changes to emdev.h (can't look at inhcount)
2007-10-04 00:00:00 -04:00
Jim
84f57c9d59 removed rounding operation from ieeepr8 - causing Info RUN to fail +
changed ARGT to add ring bits to LB & SB in brsave[]
major TRACE update, to debug Information tsrc$$ problem
changed MAXMB default for non-OSX platforms (PS3) to 32MB
2007-10-02 00:00:00 -04:00
Jim
399b67ea91 SSSN hack to bypass serialization in Primos, more performance tweaks
changed B(I,D)(X,Y) instructions to increment/decrement inside if;
  (avoids reloading values to test them) and removed B(X,Y)NE macros
changed default cpuid to 15 so real time clock is always set
use ppa instead of ppn to avoid << 10 on every memory reference
changed newkeys() so illegal keys give illegal instruction vs fatal()
removed hack to patch Primos for rev 23 SSSN check
added code to SSSN to skip the check loop immediately following
removed #ifdef FAST from a few places, just use the faster code
added code to LDA trace to also display as two octal bytes
2007-09-23 00:00:00 -04:00
Jim
2fb2e1a348 PCL fixes, more perf tweaks: shift, prtn, add16
changed EXPCL macro to set and clear bits - not just set
changed shift instructions - made CLEARCL conditional;  this
  means keys are only updated once per shift, not twice
fixed prtn to update stack free pointer after values fetched
  in case a fault occurs and prtn is restarted
changed prtn to invalidate brp cache only if ring changes
changed prtn to inline, to avoid register save/restore
changed argt to only update rp word offset in sf header
added hack to pcl to correct wrapped RP for cpu.pcl case 42
added cgt inline proc, used in 2 places; generates better code
  (store to utempa is avoided altogether)
added pimh (also used for pima) inline proc to avoid stores
inlined invalidate_brp
changed add16 implementation while looking at code generated
  ran faster according to Jeff's timers: 59/52 for old/new
2007-09-15 00:00:00 -04:00
Jim
d99d16932d More performance tweeaks: get/put(16/32)r, eaxxx()
changed get/put(16,32)r to check for ring change and use regular
  get/put call if possible, so brp supercache can be used
FUTURE: could add separate brp cache entry for R0 accesses
changed ea32r64r live register test so normal path is first
changed ea64v live register test so normal path is first
change ea32i to use INCRP macro instead of RPL++
2007-09-15 00:00:00 -04:00
Jim
91f8780e43 moved memlimit global variable to gv structure for quicker access +
removed need for duplicated memcpy in pcl() (copying ecb)
inlined pclea for speed
FUTURE: would be nice to inline complex pcl/argt, but it's called
      by CALF and ARGT instructions
2007-09-15 00:00:00 -04:00
Jim
7a713e8ea9 speedup LDC/STC, STTM CPU time fix, IMA/IRS perf, apea() perf, -DNOMEM
added 2 new rbp entries for FAR0/1; used in ldc/stc
changed IMA and IRS back to use get/put16t to make use of
  supercache instead of always doing 1 mapva
changed apea() to use brp[RPBR] for AP fetch, UNBR for indirect
added -DNOMEM to remove -mem command option and testing
fixed bug in STTM causing sporadic CPU times (negative deltas)
2007-09-14 00:00:00 -04:00
Jim
e095020a55 add access bits to brp.vpn entries, use brp cache for put16 & put32
added get32m & put32m: these always map
changed get32 and put32 to be inlined
changed mem[] references to MEM[] to allow experiments
tried using register for MEM pointer - not so great
tried using register for instcount - screwed up (very sluggish)
2007-09-12 00:00:00 -04:00
Jim
0948124f29 added "# of register sets" array, enabled multi-register set code ("ors") +
moved dispatch tables to global variable structure
2007-09-12 00:00:00 -04:00
Jim
c4f7df2944 Fine tune eap supercache, other performance optimizations +
Change tracing to show when supercache is used
Symbolic names for supercache entries
Added supercache entries for sector 0 and PB (different from RP)
Add invalidate_brp to invalidate supercache
Separate get16trap (WILL trap) from get16t (MIGHT trap)
Use supercache in get32 and various get/put routines
2007-09-10 00:00:00 -04:00
Jim
84ae6fc905 eap register and gvp->brp page cache: 5 entries for PB, SB, LB, XB, "other"
removed "char unmodified" from STLB; uses access[2] instead, to
  avoid a multiply instruction in mapva (can use shift now)
use ea instead of pa when checking for page crossing in get32,
  in preparation for read VA caching, like iget16 uses
2007-09-09 00:00:00 -04:00
Jim
98417e5835 invalidate instruction cache page (instvpn) whenever OWNER might change
removed OWNER tests from instruction fetch
2007-09-07 00:00:00 -04:00
Jim
6afd8f2c52 added inline to shift procedures (reduced the executable size, + faster) +
changed gvp->prevppa from Prime memory offset to mem[] pointer
added inline to tch, tcr, adlr
added -DNOIDLE to make BDX use CPU cycles instead of sleeping
changed ea64v.h so ixy avoids branching (hot spot in Shark)
2007-09-07 00:00:00 -04:00
Jim
24179fd2ac added dispatch table for SRV memory references instructions vs switch +
inlined and simplified iget16 instruction fetch
moved pio test to R-mode path
moved and simplified effective address calculation switch stmt
removed mode switch stmt for EA calcs, changed to cascaded if
moved iget16 static vars to gvp, for inlining
changed mapva and iget16 so that the normal path is predicted
2007-09-05 00:00:00 -04:00
Jim
31edfb6674 removed valid bit from STLB cache and use segment # 0xFFFF instead
this allows removing a comparison from mapva's fast path
2007-09-04 00:00:00 -04:00
Jim
ab4316a6a8 added FAST2 #ifdef to eliminate memory limit test, simplify CAS 2007-09-04 00:00:00 -04:00
Jim
2ee4f03291 added mapva stats 2007-09-04 00:00:00 -04:00
Jim
8f95ccc375 FDV, DFDV, FD, DFD always test for zero divisor, const mapio, fastmap
added fastmap, but it's disabled because Primos 19 won't boot
made mapio a const function
2007-09-04 00:00:00 -04:00
Jim
904ab90bd3 changed ea switch statement to multi-line if to check 64v first, get64 #FAST 2007-09-03 00:00:00 -04:00
Jim
a992b3de2f set crs[PBH] with 1 32-bit store instead of 2 16-bit stores in main loop +
changed order of 3 lines in iget16 to improve performance
2007-09-03 00:00:00 -04:00
Jim
8bdffd4e56 moved pio tests to R-mode so that V-mode doesn't check for pio
Perf increase from 12.3 MIPS to 12.5 MIPS
2007-09-03 00:00:00 -04:00
Jim
3e4c98c296 Added gvp->livereglim to speed up "live register" addressing mode tests 2007-09-02 00:00:00 -04:00
Jim
fdb4d4ae4c New ea64v, missing memory check, #ifdef FAST 2007-09-02 00:00:00 -04:00
Jim
0ea78958b0 Backout ea64v changes, PCL fixes, disabled curtrack/maxtrack check in devdisk 2007-09-01 00:00:00 -04:00
Jim
62b8229961 gvp dedicated global variable register, iget16 page cache 2007-08-31 00:00:00 -04:00
Jim
2f06bf6081 get/put64 are long long, not double, optimize fetch cycle device poll, ZSTEP
do "and" test on instcount so device poll isn't performed on every loop
added ZSTEP to eliminate ZGETC/ZPUTC common code
various FP changes
2007-08-27 00:00:00 -04:00
Jim
818697e797 added stopwatch.h (Jeff) and monitoring throughout 2007-08-27 00:00:00 -04:00
Jim
7601dcb718 INCRP, ADDRP macros, code optimization
added INCRP macro - now does 32-bit increments of RP for speed
added ADDRP macro to return RP incremented by n (CGT)
changed globals to static (didn't help speed much - thought it might)
moved around some functions
changed shift instructions to create bitmask at runtime (faster)
manually inlined mathexception (but used inline keyword in later revs)
2007-08-25 00:00:00 -04:00
Jim
8c0020d0dd get/put16t, crs/crsl macro, PowerPC register variables, tape bugs
changed get16/put16 to get16t/put16t where address trap might occur
this eliminates ea<0 test for all other non-trappable get16/put16 calls
changed crs & crsl to macros to reference a union vs 2 distinct variables
changed crs and RP to be register variables (regs.h)
fixed tape drive problems
2007-08-23 00:00:00 -04:00
Jim
24e7bfaea0 optimize with Shark, dispatch.h & label arrays, inhcount
changed generics from switch table to indirect jumps
removed redundant test of inhcount
beginning of a long series of optimizations with Shark tool
2007-08-16 00:00:00 -04:00
Jim
5bd57fb92a Garth, FP, XED, devmt, 512MB, sys console full duplex
sent to Garth around 8/15/07
supports 512MB memory
device "terminate" call
added XED emulation
more FP changes
changed devmt to emulate Kennedy tape drive & controller
devmt changes to support higher revs / fix bugs
2007-08-07 00:00:00 -04:00
Jim
29334a2945 fp.c now fp.h, FP rewrite, more CC macros: CLEARCC, SETEQ, SETLT 2007-06-25 00:00:00 -04:00
Jim
31f4e2e22e Removed os.[ch], ignore SIGPIPE, disk model support, 8 drives/controller
added CLEARCL macro to clean up code
ignore SIGPIPE so broken socket doesn't kill emulator
2007-06-08 00:00:00 -04:00
Jim
55ea18c85e register sets, PX, ZTRN, ZED, RTS, I-mode FP, R-mode MPL
added "smart" LRU code to handle multiple register sets
expanded registers to handle 8 user, 2 system (10 total)
turned off various process-exchange changes that were causing failures
only zero first 64K of memory
added emulation of ZTRN, ZED, and RTS
started I-mode floating point
make sure R-mode MPL faults to appease DIAG tests
2007-05-26 00:00:00 -04:00
Jim
f3ae6de902 STTM emulation, fatal() dumps concealed stack frames 2007-05-11 00:00:00 -04:00
Jim
edc9b077f3 IOTLB & mapio, FP register format, SVC
added IOTLB, mapio, and get/put16io macros so rev23 would boot
changed device drivers to go through IOTLB, not STLB
removed SVC Primos II emulation code
changed floating point register format to match memory
2007-05-08 00:00:00 -04:00
Jim
d306a85352 SSSN serial # hack, share shift procs, DIV/DVL overflow fix
hack to patch Primos 23K on the fly for SSSN check
added procs for all shifts so 32I can use them
fixed DIV & DVL to handle overflow correctly
2007-05-04 00:00:00 -04:00
Jim
d40c4bad82 more 32I work, zero physical memory on master clear, ICP/DCP changes
changed C-pointer ICP/DCP to use goofy/faster? Prime method to pass diags
2007-05-02 00:00:00 -04:00
Jim
29949a3390 32I instructions, share instructions between V and I modes
huge hunk of 32I instructions
generalized SETCC and LCXX macros so I-mode can use them
fixed bug in LDC where A-reg was getting trashed at end of string
made macros for many instructions so I-mode can use them
forgot to close the boot file
2007-04-30 00:00:00 -04:00
Jim
7d295a0334 corrected mapva "when to map" test, "fair" devamlc receive processing 2007-04-29 00:00:00 -04:00
Jim
319b868345 added ea32i.h include file, ea64v, devamlc, PNC
ea64v never needs to return a bit offset
added devamlc feature to set room available in user's input buffer
misc PNC changes (not working yet)
2007-04-19 00:00:00 -04:00