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481260827c066f4e77bc3f4e156e01ec62da6449
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26 Commits

Author SHA1 Message Date
wfjm
481260827c ibdr_maxisys,sys_conf ready for buffered DL,PC,LP and dz11,ibtst 
- use type code instead of boolean for sys_conf_ibd_{dl11,lp11,pc11}
- add sys_conf_ibtst (enabled in all systems)
- add sys_conf_ibd_dz11 (enabled in all systems)
 2019-03-02 09:01:02 +01:00
wfjm
913fe9b399 update message filters 
- vmfset: now tested for viv 2017.2 and 2018.3
- imfset: now tested for ISE 14.7
 2019-02-15 18:44:55 +01:00
wfjm
80fbad98c6 add resource lines for viv 2017.2 and 2018.3 2019-02-10 09:04:52 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
89732fe3e0 update xviv_msg_filter 
- add c type rules for 'count-only' filters
- add support for bitstream generation checking ([bit] section)
- update vmfsets
 2018-12-26 09:40:03 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
5d34d1fad6 ensure that essential vivado warnings are not discarded 
- xviv_msg_filter: display INFO Common 17-14 'further message disabled'
- viv_tools_build.tcl: increase message limits (all 200, some 5000)
- sys_w11a_*.vmfset: correct for thus far missed entries
 2018-12-07 19:38:32 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
90db21ac5e update vivado design vmfset files 2018-10-14 15:06:24 +02:00
wfjm
37b2d63281 finalize IDEC and PERFEXT wiring 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
 2018-10-14 15:02:45 +02:00
wfjm
c7e606d9b0 use DM_STAT_EXP for signals exported by pdp11_sys70 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
 2018-10-13 15:18:59 +02:00
wfjm
1be14ad15f Integrate dmpcnt in all w11 designs and backend 
- pdp11_sequencer: add DM_STAT_SE.(cpbusy,idec)
- pdp11_sys70: only preliminary set of signals, cache signals kludged
 2018-09-30 09:35:30 +02:00
wfjm
ff7b4fad97 integrate KW11-P in all w11 designs 2018-09-15 17:27:46 +02:00
wfjm
088f57df2c prepare w11a_V0.752 release 2018-08-26 10:03:24 +02:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
b6074a354f _ssim.vbom: fix incorrect aif target 2018-08-12 08:41:52 +02:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00
wfjm
211e1f3ff3 get vivado 2017.1 ready 
- xviv_msg_filter: add version-range tag support
- *.vmfset:
  - drop the nonsense 'Synth 8-6014' messages
  - adopt to different path used by 'Synth 8-3332' messages
 2017-06-10 11:36:32 +02:00
Walter F.J. Mueller
3d3035eb96 correct spelling 2017-04-30 15:33:23 +02:00
Walter F.J. Mueller
602893b937 comments updates 2017-04-23 18:22:20 +02:00
Walter F.J. Mueller
d466304530 add DEUNA to all sys_w11a systems 
- add ibdr_deuna to maxisys
- setup sys_conf for all systems
 2017-04-17 21:02:38 +02:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support 
- new test bench driver tbrun, give automatized test bench execution
 2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
 2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e1479d4e5d - Add Arty support (BRAM only) 
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
 2016-03-19 15:45:59 +00:00