- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
- xviv_msg_filter: add version-range tag support
- *.vmfset:
- drop the nonsense 'Synth 8-6014' messages
- adopt to different path used by 'Synth 8-3332' messages
- dmcmon has now the sta,sto,sus,res logic as rbmon and ibmon
- dmcmon does not depend on full state number generation anymore
- dmcmon missed WAIT instructions so far, has been fixed
- related changes:
- pdp11_sequencer can now return a simple instruction type based snum
- sys_w11a_n4 includes dmcmon again (now independent of dmscnt!)
- Vivado is used with -fsm_extraction one_hot. Starting with Vivado 2016.3
this triggers fsm recognition and re-coding of two gray counter modules.
This not only defeats the purpose of the gray coded counter, it also
caused some constraints to fail. Added attributes to prevent fsm extraction
- the logic of `connect_hw_server` and `get_hw_servers` changed after Vivado
2015.1. The `make <design>.vconfig` command worked up to Vivado 2016.2 due
to some recovery mechanism, and finally broke with 2016.3. Fixed the
call to `get_hw_servers`.
