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190 Commits

Author SHA1 Message Date
wfjm
9ca20e39ac get ready for V0.792 
- rtl/w11a/tb/
  - tbrun.yml: retire last tb_pdp11core_stim.dat based test
  - tb_pdp11core_stim.dat: remove file, now unused and obsolete
- tools/tcode/tcode.ecmd: ensure that unibus map window is not memory
- tools/dox/*.Doxyfile: up version
 2022-10-25 09:25:36 +02:00
wfjm
6a0031030b retire tb_pdp11core_stim.dat based tbrun tests 2022-10-24 10:53:25 +02:00
wfjm
22a2eeea9d tcode: add tests; minor changes 
- cpu_details.mac: add C1.* tests
- cpu_mmu.mac: B4.1: check stored PC in SimH and w11 case
 2022-10-23 09:47:14 +02:00
wfjm
11091f15bc tcode: add CPU mode 10 tests; minor changes 
- cpu_details.mac: fix systyp checks;
- cpu_mmu.mac: add MMR0/3 unimplented bit tests; add B4.1 and B4.2 tests
 2022-10-22 12:22:07 +02:00
wfjm
6ff9c8e57c tcode: add CPUERR tests; minor changes 
- cpu_details.mac: add section A2.* (cpuerr tests)
- tcode_exec.scmd: use 3M config; set STOP_SPA to 0
 2022-10-18 09:01:17 +02:00
wfjm
3134c8ac82 finalize fix for I space mode=1 in s_dstr_def 2022-10-06 11:25:15 +02:00
wfjm
278d2e229d pdp11_sequencer: BUGFIX: use I space for all mode=1,2,3 if reg=pc 
- tcode/cpu_mmu.mac: add test F1.1 (verify fix)

Closes #35
 2022-09-12 11:12:59 +02:00
wfjm
1644863a58 pdp11_mmu.vhd: BUGFIX: correct trap and PDR A logic 
- tools/asm-11/lib/defs_mmu.mac: rename md.a??, saner names for ACF
- tcode/cpu_mmu.mac: add E1.1, test m0.trp, pdr aia/aiw transitions (verify fix)

Closes #34
Closes #33
Closes #26
Closes #25
 2022-09-09 09:01:06 +02:00
wfjm
6820bba0e4 cpu_mmu: add C2.2 and C2.3 tests 2022-09-04 07:57:42 +02:00
wfjm
3bd23c9cd4 FIX: pdp11_mmu_mmr12: MMR1 write logic fix 
Closes #24
 2022-09-03 09:12:51 +02:00
wfjm
1b4b641d57 cpu_mmu: add D1.1: full mmr2+mmr1 test 2022-08-30 07:56:31 +02:00
wfjm
f09814e847 pdp11_psr: handle pm protection like cm 2022-08-29 11:09:43 +02:00
wfjm
4a7f5612cf sysid: encode system type 2022-08-22 08:50:07 +02:00
wfjm
48e08a5bcb ssr->mmr rename: the final cleanup 2022-08-18 09:06:43 +02:00
wfjm
6dfc0489aa *.vhd: ssr->mmr rename (files changed) [skip ci] 2022-08-16 07:56:21 +02:00
wfjm
3ebe054190 *.vhd: ssr->mmr rename (file renames) [skip ci] 2022-08-14 08:14:55 +02:00
wfjm
621c200b11 *.*pp,*.tcl: ssr->mmr rename 2022-08-10 08:04:19 +02:00
wfjm
e7d26bf06f tcode cpu_details.mac: add B*: Stress tests 2022-07-25 08:01:29 +02:00
wfjm
e1a577f26e cpu_eis.mac: add MUL,DIV odd, XOR 2022-07-21 08:10:47 +02:00
wfjm
8fe17e59b1 fix dangling ${sys_conf}; tmuconv update [skip ci] 
- rtl/sys_gen/*/*.vbom: some vbom's had undefined ${sys_conf} references
- tools/bin/tmuconv: add -t_vf -t_all; fis mnemos; add headers
 2022-07-19 07:53:26 +02:00
wfjm
e62e2fd995 cpu_eis.mac: add ASH,ASHC 2022-07-18 07:48:31 +02:00
wfjm
5d6a14f8b8 add tcode pu_badinst_nofpp.mac 2022-07-17 08:03:31 +02:00
wfjm
6b3aced4da add test_w11a_inst_quick.tcl, cpu_selftest.mac 2022-07-15 07:44:16 +02:00
wfjm
c1f2c0bfae remove Atlys support (only test designs, w11 design never done) 2022-07-14 08:01:05 +02:00
wfjm
c560147d6d cpu_basic.mac update section D,E, now complete 2022-07-13 07:57:14 +02:00
wfjm
15975d662e cpu_basic.mac update section B,C, now complete 2022-07-12 08:27:50 +02:00
wfjm
da1f0c151e Add first tcode; RtclRw11Cpu BUGFIX 
- rtl/sys_gen/w11a/*/tbrun.yml: add tcode execution
- tools/tcode: new area for add fast mac-only verification codes
- tools/tcl/rw11
  - tcodes.tcl: added, driver for tcode execution
- tools/src/librwxxtpp
  - RtclRw11Cpu.cpp: BUGFIX: quit before mem write if asm-11 error seen
 2022-07-08 08:35:39 +02:00
wfjm
1401e20a2e Some minor updates 
- rtl/vlib/rlink/tbcore/rlink_cext_dpi.c: add function prototypes
- rtl/sys_gen/tst_rlink/cmoda7/tb: add missing ssim vbom
- tools/bin
  - ti_w11: update --help text, add -ar,-n4d,-bn4d
  - tmuconv: add DEUNA defs
 2022-07-07 09:30:31 +02:00
wfjm
76bb350d97 add vlib/xlib/bufg_unisim, encapulate unisim BUFG 2022-07-06 09:34:15 +02:00
wfjm
43fc116e6e build flow now Vivado 2022.1 ready [skip ci] 2022-05-28 08:47:11 +02:00
wfjm
a5640780d9 cleanup tbrun setup, drop nexys4 and add nexys4d 2022-04-30 08:22:27 +02:00
wfjm
f25da67b91 docu updates; vmfset for Vivado 2020.1 [skip ci] 
- doc/CHANGELOG: fix user-contest label case issue (must be lower case)
- tools/oskit/*/README.md: clarify 211bsd patch level
- **/*.vmfset: now matching Vivado 2020.1
 2022-04-24 11:55:40 +02:00
wfjm
4001ddd695 docu updates; remove artys7 from tbrun.yml [skip ci] 
Closes #17
 2022-04-20 12:33:00 +02:00
wfjm
0c3d853a2b add GitHub action; code/comment cosmetics 2022-04-17 19:37:26 +02:00
wfjm
6b8c0633bc catch-up after a two years hiatus 
- drop Travis support (now defunct)
- generic_cpp.mk: use -std=c++17 (requires gcc 7.3 or later)
- RlinkPortCuff : drop libusb_set_debug (now deprecated)
- viv_tools_config.tcl: use open_hw_manager
- vbomconv: ghdl_m: use -Wl,--no-pie (for UB 18.04 gcc)
- simlib.vhd: write{oct,hex}: fix for ghdl V0.36 -Whide warnings
 2021-08-22 16:59:38 +02:00
wfjm
65a7161ca5 update and add READMEs [skip ci] 2019-09-02 15:33:24 +02:00
wfjm
78bb3a4a83 fixes for ghdl V0.36 -Whide warnings 2019-08-21 12:04:09 +02:00
wfjm
0269006dc8 docu updates [skip ci] 2019-08-11 09:50:44 +02:00
wfjm
563e230a6a get Nexys A7 working and integrated 
- rtl/bplib
  - arty/migui_arty_gsim.vhd: cosmetics
  - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
  - nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
  - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
  - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
  - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
  - */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
  - sys_w11a_arty_setup.tcl: add missing memsize definition
  - sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
 2019-08-10 19:03:47 +02:00
wfjm
7cccce5a51 rtl/sys_gen: add READMEs 2019-08-10 08:30:29 +02:00
wfjm
146fea4d79 SPDX: rest 2019-07-26 18:06:36 +02:00
wfjm
9f35e4863c SPDX: tb/*/tb_*.dat ect 2019-07-26 18:04:45 +02:00
wfjm
0ebc1c7403 SPDX: *.xdc 2019-07-26 18:03:23 +02:00
wfjm
d3cce101a7 SPDX: rtl/*/*.vhd 2019-07-12 19:01:49 +02:00
wfjm
3c92b79224 SPDX: Makefile(.ise) 2019-07-05 17:23:39 +02:00
wfjm
99e8b801f5 SPDX: *.mk 2019-07-05 17:20:44 +02:00
wfjm
aa4f3ae636 support byte access for em cacc access 
- pdp11_vmbox: support membe for em cacc access
- test_cp_membasics.tcl: add membe tests for memory accesses
 2019-06-30 11:47:18 +02:00
wfjm
c575613867 add and use rbaddr_ constants; use x"0000" notation 2019-06-09 11:22:52 +02:00
wfjm
600dd42e69 get ready for vivado 2019.1 
- sys_w11a_arty: down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
- sys_w11a_*.vmfset: add new rule for vivado 2019.1
 2019-06-07 19:44:19 +02:00
wfjm
2c049efbcf consolidate DL,LP,PC after lessons learned in DZ 
- ibdr_{dl,lp,pc}11_buf: size->fuse rename; re-organize rlim handling
- ibd_{dl,lp,pc}11/util.tcl: size->fuse rename
- tbench/{dl,lp,pc}11/test_*.tcl: size->fuse rename
- librw11/Rw11CntlDL11: size->fuse rename; use unit.StatInc[RT]x
- librw11/Rw11Cntl{LP,LP}11: size->fuse rename
 2019-06-01 09:19:02 +02:00