github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-01-12 00:43:01 +00:00
Code Issues Releases Wiki Activity
490 Commits 1 Branch 40 Tags
Commit Graph

66 Commits

Author SHA1 Message Date
wfjm
a72244728f add tb_*_dummy files [skip ci] 2023-02-07 10:25:20 +01:00
wfjm
c1f2c0bfae remove Atlys support (only test designs, w11 design never done) 2022-07-14 08:01:05 +02:00
wfjm
0c3d853a2b add GitHub action; code/comment cosmetics 2022-04-17 19:37:26 +02:00
wfjm
78bb3a4a83 fixes for ghdl V0.36 -Whide warnings 2019-08-21 12:04:09 +02:00
wfjm
0269006dc8 docu updates [skip ci] 2019-08-11 09:50:44 +02:00
wfjm
563e230a6a get Nexys A7 working and integrated 
- rtl/bplib
  - arty/migui_arty_gsim.vhd: cosmetics
  - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
  - nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
  - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
  - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
  - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
  - */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
  - sys_w11a_arty_setup.tcl: add missing memsize definition
  - sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
 2019-08-10 19:03:47 +02:00
wfjm
146fea4d79 SPDX: rest 2019-07-26 18:06:36 +02:00
wfjm
9f35e4863c SPDX: tb/*/tb_*.dat ect 2019-07-26 18:04:45 +02:00
wfjm
0ebc1c7403 SPDX: *.xdc 2019-07-26 18:03:23 +02:00
wfjm
d3cce101a7 SPDX: rtl/*/*.vhd 2019-07-12 19:01:49 +02:00
wfjm
3c92b79224 SPDX: Makefile(.ise) 2019-07-05 17:23:39 +02:00
wfjm
c575613867 add and use rbaddr_ constants; use x"0000" notation 2019-06-09 11:22:52 +02:00
wfjm
8d323848b3 Some minor updates 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
 2019-02-24 12:50:38 +01:00
wfjm
51c2cf328c add forgotten file for Arty S7 with MIG 2019-02-08 19:48:57 +01:00
wfjm
3cb0bc6924 add MIG support for Arty S7 2019-02-02 09:36:23 +01:00
wfjm
74ad445c1e Some minor updates: 
- tbrun: add --list option
- ti_w11: add add -ar,-n4d (ddr versions)
- travis: run all  sys_tst_sram,sys_w11a also for arty (cover ddr)
- tst_mig/test_mem.tcl: add low level iface tests
- comment changes
 2019-01-13 09:46:54 +01:00
wfjm
3a8da10b96 add MIG support for Nexys4 DDR 2019-01-12 09:48:18 +01:00
wfjm
cb7b906089 Add memory tester for Arty and MIG 
- sys_tst_sram_arty: add system and tb
- sramif_mig_arty: add SRAM to DDR via MIG adapter for arty
- cdc_pulse: add clock domain crossing for a slowly changing value
- cdc_vector_s0: add ENA port (now used in cdc_pulse)
- tst_mig/util.tcl: test_rwait: add optional lena argument
- viv_tools_build.tcl: downgrade SSN critical warnings to warnings
 2019-01-03 09:15:07 +01:00
wfjm
0e87dd8670 add sramif2migui: w11a SRAM to MIG UI interface core 2019-01-02 10:06:25 +01:00
wfjm
f50a85e646 add sys_tst_mig_arty system: a MIG tester 2019-01-01 22:41:44 +01:00
wfjm
14362b2a56 Add basic DDR memory support 
- arty board support
- viv_tools_build: export log and rpt generated in OOC synthesis runs
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
- migui_core_gsim: highly simplified MIG UI simulation model
 2018-12-31 10:00:14 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
e1abc27983 comment&code cosmetics; minor changes 2018-11-11 09:50:46 +01:00
wfjm
22bb8e011c reorganize dcm/mmcm/ppl sim models 
- sfs_gsim_core: new common simulation core
- {dcm,s6_cmt,s7_cmt}_sfs_gsim: use now sfs_gsim_core
- s7_cmt_sfs_tb: removed, use now sfs_gsim_core
- rtl/bplib/*/tb/tb_*: use now sfs_gsim_core
- tst_serloop/nexys*/tb/tb_tst_serloop*_n*: use now sfs_gsim_core
 2018-11-09 17:48:56 +01:00
wfjm
0913863793 comment&code cosmetics; minor changes 2018-11-03 10:30:00 +01:00
wfjm
b24fd9a3cb add Digilent Arty S7 board support 2018-08-25 07:58:05 +02:00
wfjm
286a8cdaff add forgotten tb_c7_sram_memctl 2018-08-10 22:17:22 +02:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
8c57be520f c7_sram_memctl: shorten ce and oe time 2017-07-02 14:22:20 +02:00
wfjm
62eb016ec2 add missing file; minor updates 2017-07-01 13:42:40 +02:00
wfjm
05c7d937c7 Add Digilent Cmod A7 (35 die size) support 
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
- is61wv5128bll: simple memory model (incl tb)
- sn_humanio_emu_rbus: human IO emulator
- 92-retro-usb-persistent.rules: add more board rules
- associated changes
  - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses
  - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
  - ti_rri: adopt Digilent autodetect for CmodA7
- add systems
  - tst_rlink: rlink tested
  - tst_sram: SRAM tester
  - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
 2017-06-28 22:29:09 +02:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00
wfjm
691b95c786 code cosmetics 2017-06-25 15:45:14 +02:00
wfjm
c2c192abe9 comment changes 2017-06-11 20:39:43 +02:00
wfjm
27de682629 minor docu changes 2017-06-05 23:09:02 +02:00
Walter F.J. Mueller
7977206a8b code and comment cosmetics 2017-05-07 18:54:16 +02:00
Walter F.J. Mueller
3d3035eb96 correct spelling 2017-04-30 15:33:23 +02:00
Walter F.J. Mueller
b937eb9a41 BUGFIX: resolve hangup of fx2 USB controller 
- was caused by inconsistent use of rx fifo thresholds
- adding more lines to monitor output (fsm_* lines for state tracking)
 2017-04-30 15:14:06 +02:00
Walter F.J. Mueller
7a3298a42d minor nexys4d fixes 
- correct sysid_board value for nexys4d
- add missing file
 2017-01-05 00:23:06 +01:00
Walter F.J. Mueller
0e96fa106b added preliminary and FPFA untested(!) support for nexys4 DDR board 
- rtl/bplib/nexys4d: added board support
- rtl/sys_gen
  - tst_rlink/nexys4d: rlink tester design
  - tst_serloop/nexys4d: serial port tester design
  - tst_snhumanio/nexys4d: human IO tester design
  - w11a/nexys4d_bram: w11 design using BRAM only
 2017-01-04 22:12:29 +01:00
Walter F.J. Mueller
92e149437d Fix license disclaimer 2016-12-26 21:27:33 +01:00
Walter F.J. Mueller
51cb648e54 docu tune-ups; some more README.md 2016-12-23 15:51:48 +01:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support 
- new test bench driver tbrun, give automatized test bench execution
 2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
 2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e1479d4e5d - Add Arty support (BRAM only) 
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
 2016-03-19 15:45:59 +00:00
Walter F.J. Mueller
677773d123 - Add CPU debug and monitoring units (dmhbpt,dmscnt,dmcmon) 2015-12-30 20:21:18 +00:00
Walter F.J. Mueller
4a032e9436 - added RH70/RP/RM big disk support 
- many cleanups
 2015-05-14 17:00:36 +00:00