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1be7bb037670c9803a6bb2ec7554bf93bbeaf25a
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89 Commits

Author SHA1 Message Date
wfjm
da1f0c151e Add first tcode; RtclRw11Cpu BUGFIX 
- rtl/sys_gen/w11a/*/tbrun.yml: add tcode execution
- tools/tcode: new area for add fast mac-only verification codes
- tools/tcl/rw11
  - tcodes.tcl: added, driver for tcode execution
- tools/src/librwxxtpp
  - RtclRw11Cpu.cpp: BUGFIX: quit before mem write if asm-11 error seen
 2022-07-08 08:35:39 +02:00
wfjm
76bb350d97 add vlib/xlib/bufg_unisim, encapulate unisim BUFG 2022-07-06 09:34:15 +02:00
wfjm
43fc116e6e build flow now Vivado 2022.1 ready [skip ci] 2022-05-28 08:47:11 +02:00
wfjm
a5640780d9 cleanup tbrun setup, drop nexys4 and add nexys4d 2022-04-30 08:22:27 +02:00
wfjm
f25da67b91 docu updates; vmfset for Vivado 2020.1 [skip ci] 
- doc/CHANGELOG: fix user-contest label case issue (must be lower case)
- tools/oskit/*/README.md: clarify 211bsd patch level
- **/*.vmfset: now matching Vivado 2020.1
 2022-04-24 11:55:40 +02:00
wfjm
4001ddd695 docu updates; remove artys7 from tbrun.yml [skip ci] 
Closes #17
 2022-04-20 12:33:00 +02:00
wfjm
0c3d853a2b add GitHub action; code/comment cosmetics 2022-04-17 19:37:26 +02:00
wfjm
65a7161ca5 update and add READMEs [skip ci] 2019-09-02 15:33:24 +02:00
wfjm
0269006dc8 docu updates [skip ci] 2019-08-11 09:50:44 +02:00
wfjm
563e230a6a get Nexys A7 working and integrated 
- rtl/bplib
  - arty/migui_arty_gsim.vhd: cosmetics
  - nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH; InputClk 100 MHz
  - nexys4d/migui_nexys4d_gsim.vhd: cosmetics
- rtl/sys_gen
  - tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
  - tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
  - w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
  - */nexys4*/tb/tbrun.yml: drop n4 from, add n4d to default
- tools/exptest/sys
  - sys_w11a_arty_setup.tcl: add missing memsize definition
  - sys_w11a_{br_arty,br_n4d,n4d}_setup.tcl: added
 2019-08-10 19:03:47 +02:00
wfjm
d3cce101a7 SPDX: rtl/*/*.vhd 2019-07-12 19:01:49 +02:00
wfjm
3c92b79224 SPDX: Makefile(.ise) 2019-07-05 17:23:39 +02:00
wfjm
600dd42e69 get ready for vivado 2019.1 
- sys_w11a_arty: down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
- sys_w11a_*.vmfset: add new rule for vivado 2019.1
 2019-06-07 19:44:19 +02:00
wfjm
ad82539ad8 minor changes and docu updates 2019-05-29 17:48:47 +02:00
wfjm
6c7fa2fd11 sys_conf: prepare for m9312 2019-05-05 08:28:30 +02:00
wfjm
1c9dbeb4ed dl11_buf: buffered DL11; add tbench 
- ibdr_dl11_buf: new DL11 interface with fifo buffering
- ibdr_dl11: drop rbuf.rrdy, set rbuf.[rx]size0 instead
- ibdr_maxisys: add ibdr_dl11_buf
- librw11/RtraceTools: new, some helper methods for buffer tracing
- librw11/Rw11CntlDL11: add dl11_buf readout
- librwxxtpp/RtclRw11CntlDL11: add getters& setters for dl11_buf readout
- ibd_dl11/util.tcl: setup defs for dl11_buf; add rdump proc
- rw11/util.tcl: setup_tt: add dl{rxqlim,txrlim}; dlrrlim->dlrxrlim
- oskit/*/*_boot.tcl: setup dlrxrlim
- tbench/dl11: tbench for dl11(_buf)
 2019-04-28 12:51:58 +02:00
wfjm
785016763f pc11_buf: buffered PC11; add lp11,pc11 mcodes 2019-04-24 12:59:58 +02:00
wfjm
f9faf937b1 lp11_buf: output buffered; add tbench 
- ib_rlim_{gen,slv}: new modules for implementation of rate limiters
- ibdr_lp11_buf: new LP11 interface with fifo buffering
- ibdr_maxisys: add ib_rlim_gen, ibdr_lp11_buf
- tbench/test_lp11_all.tcl: tbench for lp11 and lp11_buf
- Rw11CntlLP11: handles now also buffered lp11
 2019-03-23 08:20:25 +01:00
wfjm
e14d92f9cc comment&code cosmetics 2019-03-08 16:44:44 +01:00
wfjm
481260827c ibdr_maxisys,sys_conf ready for buffered DL,PC,LP and dz11,ibtst 
- use type code instead of boolean for sys_conf_ibd_{dl11,lp11,pc11}
- add sys_conf_ibtst (enabled in all systems)
- add sys_conf_ibd_dz11 (enabled in all systems)
 2019-03-02 09:01:02 +01:00
wfjm
8d323848b3 Some minor updates 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
 2019-02-24 12:50:38 +01:00
wfjm
913fe9b399 update message filters 
- vmfset: now tested for viv 2017.2 and 2018.3
- imfset: now tested for ISE 14.7
 2019-02-15 18:44:55 +01:00
wfjm
80fbad98c6 add resource lines for viv 2017.2 and 2018.3 2019-02-10 09:04:52 +01:00
wfjm
39a6280cda remove iist from Spartan-3,6 designs 2019-02-09 09:13:46 +01:00
wfjm
c47ac81e78 down rate sys_w11a_arty to 75 Mhz for viv 2018.3 2019-02-08 20:30:19 +01:00
wfjm
f613babe57 add w11a system for Arty S7 with MIG 2019-02-03 09:23:05 +01:00
wfjm
302dc20cb7 add w11a system for Nexys4 DDR with MIG 2019-01-27 09:54:19 +01:00
wfjm
74ad445c1e Some minor updates: 
- tbrun: add --list option
- ti_w11: add add -ar,-n4d (ddr versions)
- travis: run all  sys_tst_sram,sys_w11a also for arty (cover ddr)
- tst_mig/test_mem.tcl: add low level iface tests
- comment changes
 2019-01-13 09:46:54 +01:00
wfjm
dd7cdfeceb add w11a system for Arty with MIG 2019-01-04 09:19:00 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
89732fe3e0 update xviv_msg_filter 
- add c type rules for 'count-only' filters
- add support for bitstream generation checking ([bit] section)
- update vmfsets
 2018-12-26 09:40:03 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
5d34d1fad6 ensure that essential vivado warnings are not discarded 
- xviv_msg_filter: display INFO Common 17-14 'further message disabled'
- viv_tools_build.tcl: increase message limits (all 200, some 5000)
- sys_w11a_*.vmfset: correct for thus far missed entries
 2018-12-07 19:38:32 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
90db21ac5e update vivado design vmfset files 2018-10-14 15:06:24 +02:00
wfjm
37b2d63281 finalize IDEC and PERFEXT wiring 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
 2018-10-14 15:02:45 +02:00
wfjm
c7e606d9b0 use DM_STAT_EXP for signals exported by pdp11_sys70 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
 2018-10-13 15:18:59 +02:00
wfjm
1be14ad15f Integrate dmpcnt in all w11 designs and backend 
- pdp11_sequencer: add DM_STAT_SE.(cpbusy,idec)
- pdp11_sys70: only preliminary set of signals, cache signals kludged
 2018-09-30 09:35:30 +02:00
wfjm
4df1d3e549 minor comment corrections/additions 2018-09-21 19:35:31 +02:00
wfjm
ff7b4fad97 integrate KW11-P in all w11 designs 2018-09-15 17:27:46 +02:00
wfjm
40d48680e9 finalize w11a_V0.752 release 2018-08-26 13:54:48 +02:00
wfjm
088f57df2c prepare w11a_V0.752 release 2018-08-26 10:03:24 +02:00
wfjm
010c79c0fc add w11a port to Arty S7 (BRAM only, sim-tested only) 2018-08-25 07:59:59 +02:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
b6074a354f _ssim.vbom: fix incorrect aif target 2018-08-12 08:41:52 +02:00
wfjm
5493c0f4f2 minor docu updates, add INSTALL_quickstart 2018-08-04 15:07:12 +02:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
62eb016ec2 add missing file; minor updates 2017-07-01 13:42:40 +02:00
wfjm
05c7d937c7 Add Digilent Cmod A7 (35 die size) support 
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
- is61wv5128bll: simple memory model (incl tb)
- sn_humanio_emu_rbus: human IO emulator
- 92-retro-usb-persistent.rules: add more board rules
- associated changes
  - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses
  - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
  - ti_rri: adopt Digilent autodetect for CmodA7
- add systems
  - tst_rlink: rlink tested
  - tst_sram: SRAM tester
  - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
 2017-06-28 22:29:09 +02:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00