50 Commits

Author	SHA1	Message	Date
Andrew Kay	a137b00b0d	Update pin assignments for new development board	2020-08-24 08:28:20 -05:00
Andrew Kay	6e9a981064	Fix bug in TX start sequence generation	2020-07-31 17:48:15 -05:00
Andrew Kay	8dc730df8a	Fix receiver start and end sequence detection	2020-07-10 22:15:53 -05:00
Andrew Kay	4fa9e0381b	Headers	2020-07-09 18:51:38 -05:00
Andrew Kay	32419dd760	Disable receiver input when not enabled	2020-07-09 17:21:30 -05:00
Andrew Kay	28fc1c0cef	Add distortion	2020-07-09 07:50:24 -05:00
Andrew Kay	7fd767a8cd	Consistency	2020-07-08 21:42:05 -05:00
Andrew Kay	411cd847dc	Integrate coax_tx into top	2020-07-08 19:58:23 -05:00
Andrew Kay	f2166cd960	Add initial coax_tx	2020-07-08 19:19:19 -05:00
Andrew Kay	095f1a3ba5	Add coax_tx_bit_timer	2020-07-08 16:17:17 -05:00
Andrew Kay	9942a9e2c4	register active and error	2020-07-06 20:07:58 -05:00
Andrew Kay	e2974b2365	Implement read	2020-07-05 18:56:36 -05:00
Andrew Kay	d8464625e7	Cleanup internal_data name	2020-07-05 17:00:19 -05:00
Andrew Kay	9d8d1aa41a	Cleanup, maybe, state_counter	2020-07-05 16:59:45 -05:00
Andrew Kay	c155c23d5f	Add data bus	2020-07-05 16:43:39 -05:00
Andrew Kay	c49a82f588	First hardware test of coax_rx, increase clk frequency	2020-07-05 16:13:36 -05:00
Andrew Kay	eacb8f0eea	Work in progress	2020-07-05 14:41:33 -05:00
Andrew Kay	2bf4c85126	More work in progress	2020-07-05 13:46:45 -05:00
Andrew Kay	90ddeb54d6	Work in progress	2020-07-05 13:00:46 -05:00
Andrew Kay	ed4ca3024d	some progress...	2020-07-04 16:57:46 -05:00
Andrew Kay	293609fc6c	wip	2020-06-23 20:27:12 -05:00
Andrew Kay	d3ca7a1d45	testing rx_coax_bit_timer on TinyFPGA	2020-06-21 18:52:21 -05:00
Andrew Kay	9dd8d37ef5	wip	2020-06-16 16:53:53 -05:00
Andrew Kay	0a03fde6f9	Initial coax_rx_bit_timer	2020-06-15 21:22:30 -05:00
Andrew Kay	03af715ec5	Start over	2020-06-14 10:05:02 -05:00
Andrew Kay	6ca7b6ba0e	Add receiver enable	2020-03-28 18:06:20 -05:00
Andrew Kay	0785407a49	Add TX to top	2020-03-13 21:26:13 -05:00
Andrew Kay	b750c9e756	Drop shims, for now	2020-03-03 19:52:56 -06:00
Andrew Kay	891390cb84	Attempt DP8340 and DP8341 shims	2020-02-21 20:43:52 -06:00
Andrew Kay	49abcf7e2b	Add data, data_available and data_read	2020-02-18 07:55:13 -06:00
Andrew Kay	811a048685	Initial attempt at receiver	2020-02-17 20:47:46 -06:00
Andrew Kay	2b81a4a961	Clean up bit timer	2020-02-15 09:41:37 -06:00
Andrew Kay	81c6172e7b	Bit timer module	2020-02-14 20:13:01 -06:00
Andrew Kay	a95e83bd5e	Clean up full and data loading	2020-02-14 07:58:14 -06:00
Andrew Kay	a8f0949842	Parameterize tx_delay_buffer size	2020-02-14 06:57:50 -06:00
Andrew Kay	a7ee9c502d	Add tx_delay size comment	2020-02-13 19:26:17 -06:00
Andrew Kay	d4eaeecec2	Hello world	2020-02-12 23:13:21 -06:00
Andrew Kay	c859688931	Initial attempts at multiple word transmission	2020-02-12 19:44:43 -06:00
Andrew Kay	cc7023d35f	Cleanup	2020-02-11 07:51:10 -06:00
Andrew Kay	13eb0f52bd	Adding tx_inverted and updating pins	2020-02-10 22:26:39 -06:00
Andrew Kay	ff200bf26f	Adding tx_delay	2020-02-10 22:13:55 -06:00
Andrew Kay	7bf43eede5	Remove BIT_ALIGN state and improve active	2020-02-10 21:56:35 -06:00
Andrew Kay	05663ab5b7	End sequence	2020-02-09 14:53:23 -06:00
Andrew Kay	7a78447c6c	Cleanup clocks	2020-02-09 09:50:40 -06:00
Andrew Kay	42a46806c8	Parity bit	2020-02-09 09:35:00 -06:00
Andrew Kay	77821b3f11	Data	2020-02-08 20:03:13 -06:00
Andrew Kay	b9ed29bd4b	Code violation and sync bit	2020-02-08 19:03:36 -06:00
Andrew Kay	9faae78fd8	Quiesce pattern	2020-02-08 18:55:11 -06:00
Andrew Kay	0b618d6b35	Adding a 19 MHz clock	2020-02-08 17:43:09 -06:00
Andrew Kay	ad7ba12d2c	Verilog templating	2020-02-04 22:11:14 -06:00