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481260827c066f4e77bc3f4e156e01ec62da6449
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70 Commits

Author SHA1 Message Date
wfjm
481260827c ibdr_maxisys,sys_conf ready for buffered DL,PC,LP and dz11,ibtst 
- use type code instead of boolean for sys_conf_ibd_{dl11,lp11,pc11}
- add sys_conf_ibtst (enabled in all systems)
- add sys_conf_ibd_dz11 (enabled in all systems)
 2019-03-02 09:01:02 +01:00
wfjm
8d323848b3 Some minor updates 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
 2019-02-24 12:50:38 +01:00
wfjm
913fe9b399 update message filters 
- vmfset: now tested for viv 2017.2 and 2018.3
- imfset: now tested for ISE 14.7
 2019-02-15 18:44:55 +01:00
wfjm
80fbad98c6 add resource lines for viv 2017.2 and 2018.3 2019-02-10 09:04:52 +01:00
wfjm
39a6280cda remove iist from Spartan-3,6 designs 2019-02-09 09:13:46 +01:00
wfjm
c47ac81e78 down rate sys_w11a_arty to 75 Mhz for viv 2018.3 2019-02-08 20:30:19 +01:00
wfjm
f613babe57 add w11a system for Arty S7 with MIG 2019-02-03 09:23:05 +01:00
wfjm
302dc20cb7 add w11a system for Nexys4 DDR with MIG 2019-01-27 09:54:19 +01:00
wfjm
74ad445c1e Some minor updates: 
- tbrun: add --list option
- ti_w11: add add -ar,-n4d (ddr versions)
- travis: run all  sys_tst_sram,sys_w11a also for arty (cover ddr)
- tst_mig/test_mem.tcl: add low level iface tests
- comment changes
 2019-01-13 09:46:54 +01:00
wfjm
dd7cdfeceb add w11a system for Arty with MIG 2019-01-04 09:19:00 +01:00
wfjm
b8dfa6d41e get ready for w11a_V0.753 release 
- rtl/sys_gen/*/*.vhd: drop superfluous genlib call
- rtl/sys_gen/*/*.vmfset: accomodate recent code changes
- tools/bin/tbrun: show correct 'found count' in summary message
- tools/dox/*.Doxyfile: push version to 0.753
- tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
 2018-12-29 14:14:08 +01:00
wfjm
89732fe3e0 update xviv_msg_filter 
- add c type rules for 'count-only' filters
- add support for bitstream generation checking ([bit] section)
- update vmfsets
 2018-12-26 09:40:03 +01:00
wfjm
674762d6d8 consolidate clock generation in 7-Series designs 
- s7_cmt_1ce1ce: add clock generator block used in many 7-Series designs
- sys_gen/*/*: use s7_cmt_1ce1ce in 7-Series designs
- tbcore_rlink: wait 40 cycles after CONF_DONE
- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
 2018-12-21 09:06:16 +01:00
wfjm
5d34d1fad6 ensure that essential vivado warnings are not discarded 
- xviv_msg_filter: display INFO Common 17-14 'further message disabled'
- viv_tools_build.tcl: increase message limits (all 200, some 5000)
- sys_w11a_*.vmfset: correct for thus far missed entries
 2018-12-07 19:38:32 +01:00
wfjm
a3bf3519d9 remove ISE build support for 7Series designs 2018-12-01 13:07:59 +01:00
wfjm
90db21ac5e update vivado design vmfset files 2018-10-14 15:06:24 +02:00
wfjm
37b2d63281 finalize IDEC and PERFEXT wiring 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
 2018-10-14 15:02:45 +02:00
wfjm
c7e606d9b0 use DM_STAT_EXP for signals exported by pdp11_sys70 
- pdp11_sys70: drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
- pdp11_sequencer: drop ITIMER port, use DM_STAT_SE.itimer
- sys_w11a_*.vhd: use DM_STAT_EXP
- some re-wiring, no functional change to CPU or IO system
 2018-10-13 15:18:59 +02:00
wfjm
1be14ad15f Integrate dmpcnt in all w11 designs and backend 
- pdp11_sequencer: add DM_STAT_SE.(cpbusy,idec)
- pdp11_sys70: only preliminary set of signals, cache signals kludged
 2018-09-30 09:35:30 +02:00
wfjm
4df1d3e549 minor comment corrections/additions 2018-09-21 19:35:31 +02:00
wfjm
ff7b4fad97 integrate KW11-P in all w11 designs 2018-09-15 17:27:46 +02:00
wfjm
40d48680e9 finalize w11a_V0.752 release 2018-08-26 13:54:48 +02:00
wfjm
088f57df2c prepare w11a_V0.752 release 2018-08-26 10:03:24 +02:00
wfjm
010c79c0fc add w11a port to Arty S7 (BRAM only, sim-tested only) 2018-08-25 07:59:59 +02:00
wfjm
ac16d6d27e *.vmfset: update rules to cover 2017.4-2018.2 2018-08-24 20:52:21 +02:00
wfjm
b6074a354f _ssim.vbom: fix incorrect aif target 2018-08-12 08:41:52 +02:00
wfjm
5493c0f4f2 minor docu updates, add INSTALL_quickstart 2018-08-04 15:07:12 +02:00
wfjm
dfa2a91a18 get disclaimers in line with GPL V3 License.txt 2018-01-02 21:57:40 +01:00
wfjm
62eb016ec2 add missing file; minor updates 2017-07-01 13:42:40 +02:00
wfjm
05c7d937c7 Add Digilent Cmod A7 (35 die size) support 
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
- is61wv5128bll: simple memory model (incl tb)
- sn_humanio_emu_rbus: human IO emulator
- 92-retro-usb-persistent.rules: add more board rules
- associated changes
  - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses
  - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity
  - ti_rri: adopt Digilent autodetect for CmodA7
- add systems
  - tst_rlink: rlink tested
  - tst_sram: SRAM tester
  - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)
 2017-06-28 22:29:09 +02:00
wfjm
4aa1db49c7 Cleanups; 17bit support for tst_sram 
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
 2017-06-25 20:20:48 +02:00
wfjm
691b95c786 code cosmetics 2017-06-25 15:45:14 +02:00
wfjm
97f1539292 add test_w11a_mem70.tcl; retire old tests tb_w11a_mem70*.dat 2017-06-25 15:43:19 +02:00
wfjm
211e1f3ff3 get vivado 2017.1 ready 
- xviv_msg_filter: add version-range tag support
- *.vmfset:
  - drop the nonsense 'Synth 8-6014' messages
  - adopt to different path used by 'Synth 8-3332' messages
 2017-06-10 11:36:32 +02:00
wfjm
5d3504b01a documentation updates 2017-06-04 09:08:37 +02:00
Walter F.J. Mueller
3d3035eb96 correct spelling 2017-04-30 15:33:23 +02:00
Walter F.J. Mueller
eb53dc6bfd use SWI(7:6) to allow fx2 debug via LEDs 2017-04-30 15:14:56 +02:00
Walter F.J. Mueller
602893b937 comments updates 2017-04-23 18:22:20 +02:00
Walter F.J. Mueller
d14626ce29 dmcmon: new interface, proper wait handling, vivado friendly 
- dmcmon has now the sta,sto,sus,res logic as rbmon and ibmon
- dmcmon does not depend on full state number generation anymore
- dmcmon missed WAIT instructions so far, has been fixed
- related changes:
  - pdp11_sequencer can now return a simple instruction type based snum
  - sys_w11a_n4 includes dmcmon again (now independent of dmscnt!)
 2017-04-23 18:13:52 +02:00
Walter F.J. Mueller
1ba7b70891 use sys_conf_dmcmon_awidth=8 (proper value) 2017-04-23 18:02:07 +02:00
Walter F.J. Mueller
d466304530 add DEUNA to all sys_w11a systems 
- add ibdr_deuna to maxisys
- setup sys_conf for all systems
 2017-04-17 21:02:38 +02:00
Walter F.J. Mueller
a2264ab463 23 line interrupt mapper for full system configuration 2017-01-29 14:08:04 +01:00
Walter F.J. Mueller
7a3298a42d minor nexys4d fixes 
- correct sysid_board value for nexys4d
- add missing file
 2017-01-05 00:23:06 +01:00
Walter F.J. Mueller
0e96fa106b added preliminary and FPFA untested(!) support for nexys4 DDR board 
- rtl/bplib/nexys4d: added board support
- rtl/sys_gen
  - tst_rlink/nexys4d: rlink tester design
  - tst_serloop/nexys4d: serial port tester design
  - tst_snhumanio/nexys4d: human IO tester design
  - w11a/nexys4d_bram: w11 design using BRAM only
 2017-01-04 22:12:29 +01:00
Walter F.J. Mueller
b2e7c1cdbb rw11::shell.tcl now default environemnt in ti_w11 
- tools/bin/ti_w11: use rw11::shell by default; add -ns to suppress it
- tools/oskit/*/*_boot.tcl: remove activation of cpucons and cpumon
- tools/src/librwxxtpp
  - RtclRw11Cpu.cpp: use 'ssr' instead of 'mmr' for MMU register names
- tools/tcl/rw11:
  - defs.tcl: fix typo in regmap_add for SDR's
  - shell.tcl: add '@' command
  - shell_simh.tcl: added, simh command converter
- *: README updates
 2016-12-31 11:04:22 +01:00
Walter F.J. Mueller
238b6e4276 rename .cvsignore -> .gitignore 2016-12-17 16:28:37 +01:00
Walter F.J. Mueller
5983b0bb2a - upgraded CRAM controller, now with 'page mode' support 
- new test bench driver tbrun, give automatized test bench execution
 2016-10-15 07:42:21 +00:00
Walter F.J. Mueller
2b5cfb7d96 - Code base cleaned-up for vivado, fsm now inferred 
- xsim support complete (but many issues to be resolved yet)
- Added configurable w11a cache
- Removed some never documented and now strategically obsolete designs
 2016-06-26 16:02:42 +00:00
Walter F.J. Mueller
e1479d4e5d - Add Arty support (BRAM only) 
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
 2016-03-19 15:45:59 +00:00
Walter F.J. Mueller
677773d123 - Add CPU debug and monitoring units (dmhbpt,dmscnt,dmcmon) 2015-12-30 20:21:18 +00:00